cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Newbie
Newbie
319 Views
Registered: ‎04-30-2020

Warning on zynqmp_fsbl

Trying to run through some tutorials and examples, to get a better understanding of the Zynq. I'm currently using the Avnet Ultra96V2, Vivado 2019.2 and Vitis 2019.2. 

I'm currently having an issue while trying to work through this example: https://www.hackster.io/anujvaishnav20/programming-rtl-accelerators-via-axi-slave-wrappers-8c64cf 

When I attempt to run Hello World on the Ultra96, using the hardware platform built in the above example, I get the warning message attached about FSBL not exiting.

I note when building the platform project, I have 6 warnings (see attachment). 

When running through the Ultra96 tutorials, I did not experience this issue. However, now if I run through these tutorials again, I note that I see the same warnings. It feels like this should be simple to resolve, but can't work it out. 

Any help, much appreciated. 

Capture2.jpg
Capture1.JPG
0 Kudos
Reply
1 Reply
Xilinx Employee
Xilinx Employee
224 Views
Registered: ‎10-06-2016

Hi @aaxl 

Not sure if you already solved the issue but in general the pop-up warning message is just stating that the breakpoint placed on the predefined location has not been reached.

In Vitis the debug configuration generated in the IDE by default makes use of the FSBL to initialize the device, and in the initialization process is expected that the execution of the FSBL will reach the exit function within 60 seconds. If it is not reaching this point likely could be due to the device boot mode not being JTAG, which will make the FSBL to execute a different flow.

Regards


Ibai
Don’t forget to reply, kudo, and accept as solution.
0 Kudos
Reply