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Visitor c.akronbt
Visitor
6,707 Views
Registered: ‎12-14-2015

Xilinx Uart 16550

Hello,

 

I have a Microblaze system with an Xilinx Uart 16550 connected. The uart is setup with FIFO enabled and 8 byte of threshold.
Reading the manual of uart I expect an ISR when 8 byte has received into the FIFO but this don't happening, I have an ISR at every byte received.

The configuration code of uart is:

 

	XUartNs550_SetBaudRate(UartInstancePtr,baudrate);
	XUartNs550_WriteReg(UartInstancePtr->BaseAddress,XUN_MCR_OFFSET,0x02);			//XUN_MCR_RTS
	XUartNs550_WriteReg(UartInstancePtr->BaseAddress,XUN_LCR_OFFSET,0x03);			//XUN_LCR_8_DATA_BITS & ~XUN_LCR_LENGTH_MASK & ~XUN_LCR_ENABLE_PARITY
	XUartNs550_WriteReg(UartInstancePtr->BaseAddress,XUN_IER_OFFSET,0x01);			//XUN_IER_RX_DATA
	XUartNs550_WriteReg(UartInstancePtr->BaseAddress,XUN_FCR_OFFSET,0x47);			//XUN_FIFO_TRIGGER_08 | XUN_FIFO_ENABLE | XUN_FIFO_RX_RESET | XUN_FIFO_TX_RESET

Can anyone help me?

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3 Replies
Scholar austin
Scholar
6,674 Views
Registered: ‎02-27-2008

Re: Xilinx Uart 16550

c,

 

Nowhere do I see a feature to provide an interrupt when the FIFO has 8 characters described in the manual.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor c.akronbt
Visitor
6,512 Views
Registered: ‎12-14-2015

Re: Xilinx Uart 16550

Thanks for the reply.

I have solved the problem!

 

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Xilinx Employee
Xilinx Employee
6,465 Views
Registered: ‎08-02-2007

Re: Xilinx Uart 16550

hi,

 

can you mark this post as solved and also let us know how this problem was solved. this will help out other users

 

--hs

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