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672 Views
Registered: ‎08-28-2019

Xilinx & Vivado, frustration

I am using both 2016.2 and 2019.1 versions of Xilinx with an already existing product.  Some bits work in 2019.1 and not in 2016.2, some bits work in 2016.2 and not 2019.1

In 2016.2 the application builds and can be deployed, however for some reason we cannot debug the application using the 2016 IDE and all we get is assembler.

In 2019.1 the application builds and can be deployed, with this we can debug and read the source, however this crashes because the application shares a resource with an FPGA and when this is access the application crashes.  This is exactly the same on 2016 but it doesn't crash.

For 2016.2 Vivado was used to configure the memory, this hasn't been done for 2019 and we are having problems loading the project files from 2016 to 2019.

It could be human error, although the people behind the original implementations have moved on, the IDE's both 2016 and 2019 are flawed in various ways and are not very user friendly, when an action is clicked there is no status or feedback, it just goes away and does something in the background with no status then "might" come back with an error message.

There does not appear to be any forward migration or fixes and all the paths seem to be absolute and broken which is something else that breaks everything.

I need to get the system up and running, ideally with 2019.2 but I cannot launch Vivado 2019 with the 2016 project files.  It's less than satisfactory.

Kind Regards,
Sy
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12 Replies
669 Views
Registered: ‎07-23-2019

Re: Xilinx & Vivado, frustration


simon.platten@buhlergroup.com wrote:

I am using both 2016.2 and 2019.1 versions of Xilinx with an already existing product.  Some bits work in 2019.1 and not in 2016.2, some bits work in 2016.2 and not 2019.1


As a venting exercise, it's fine. Now, if you specify what Xilinx products are these (ISE, Vivado, SDK...), what (or what type) your 'existing product' is (VHDL/ Verilog, block diagram, IP core, bare metal software, Linux based software,...) and what are those non-working bits, then, knowing that, we might as well be able to help.

 

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655 Views
Registered: ‎08-28-2019

Re: Xilinx & Vivado, frustration

What information would you like?

From the various about dialogs:

Xilinx Software Development Kit, Release Version: 2019.1

Vivado, v2019.1 (64-bit), SW Build: 2552052, IP Build: 2548770

Xilinx Software Development Kit, Release Version: 2016.2

Vivado, v2016.2 (64-bit), SW Build: 1577090, IP Build: 1577682

The host platform is running Windows 10, however the target is a Zynq Zybo board.

 

Kind Regards,
Sy
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633 Views
Registered: ‎07-23-2019

Re: Xilinx & Vivado, frustration

simon.platten@buhlergroup.com 

Xilinx is (un)famous for not being fully (even worse than un-) compatible between releases.

I feel your frustration with Vivado. When it comes to SDK, it could be for the included libraries changing (presumably for good) and you using system functions that have changed in these three years.

 

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628 Views
Registered: ‎08-28-2019

Re: Xilinx & Vivado, frustration

Oher really annoying things are that when trying to create a debug configuration , oftern a Java error will come up, Java has been updated to the latest, however this hasn't helped either.

So I'm trying to get the project debuggable in 2019.2 on the target...I click on "Debug configurations...", then highlight "Xilinix C/C++ application (System Debugger)" and click on the icon to add a new configuration.

The default assigned name is "System Debugger on Local", I change the "Debug Type" drop down to "Standalong Application Debug".  Settings default to:

"Hardware Platform" "design_hsorter_wrapper_hw_platform_0"

"Bitstream File" "design_1_wrapper.bit"

"Initialization File" "ps7_init.tcl"

"FPGA Device" "Auto Detect"

On the Application tab:

Checked "Stop at 'main'

Checked in Summary "Download ps7_cortexa9_0 FSBL_port"

Project name FSBL_port

"PS Device" "Auto Detect"

Checked boxes, Program FPGA, Run ps7_init

 

 

Kind Regards,
Sy
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616 Views
Registered: ‎07-23-2019

Re: Xilinx & Vivado, frustration

I also have frequent and unexplainable errors that save me a lot of money in hair cutting (LoL) but not java pop-ups... it could be not-Xilinx related but just your machine stack of applications (I know that's the second silliest thing after 'have you power cycled it?'). Do you have another PC to try? I know most of don't have time to faff around with PCs...

My take is the FSBL is most of times untouched and what you write and debug is the application, so you need to download both and debug the application:

err1.png

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607 Views
Registered: ‎08-28-2019

Re: Xilinx & Vivado, frustration

The PC has been reset several times and sometimes the Java error doesn't come up, but I think this is a cunning ploy to make you feel better then it drop kicks you in the gut just as you think you might be winning.

Kind Regards,
Sy
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575 Views
Registered: ‎07-23-2019

Re: Xilinx & Vivado, frustration

i didn't mean reset but having a fresh install of OS and everything. I know it's painful but sometimes machines get software screwed up. I have many errors with the Xilinx tools (including surprise shutdowns) but not any java pop-up

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374 Views
Registered: ‎08-28-2019

Re: Xilinx & Vivado, frustration

I created this post once already today, no idea where it went but it disappeared.

The functionality I want to replicate works for the 2016.2 build but not for the 2019.1 build.  In the 2016.2 build Vivado 2016.2 was used to enable the FPGA and application to share an area of memory.  The memory starts at location:

        //Axi Address
        #define AXI_ADDRESS_MAPPING 0x43c00000

A structure has been created which points to this address:

        //AXI Mapping to FPGA Registers
        typedef struct AxiAddress {
              u32_t EjectionDecision[EJD] /* Mapping 0-3 */
                       ,SelectInternalEOS /* Mapping 4 */
                       ,EjectionYExtension /* Mapping 5 */
                       ,SetEjectionDelay /* Mapping 6 */
                       ,EnableEjectors /* Mapping 7 */
                       ,Select128Ejectors /* Mapping 8 */
                       ,SetReverseOrder /* Mapping 9 */
                       ,EjectionWidthExtension /* Mapping 10 */
                       ,SyncExtension /* Mapping 11 */
                       ,EjectorTestMode /* Mapping 12 */
                       ,EjectorTestFrequency /* Mapping 13 */
                       ,EjectorTestRegister[EJD] /* Mapping 14-17 */
                       ,FpgaVersion /* Mapping 18 */
                       ,SynchCounter[2] /* Mapping 19-20 */
                       ,ResetSynchCounter; /* Mapping 21 */
              } AxiAddressMapping;

The application writes to this structure and in the 2016 version of the application it works, in the 2019 version of the application it doesn't work.  I believe I have to run Vivado 2019 and set up the address to allow the 2019 application to work, problem is I have no experience of this and need help.

 

Is there a tutorial or good source of information on how to do this?  I'm not sure why the process differs from 2016 to 2019, but it must as the 2019 build doesn't work.

Kind Regards,
Sy
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362 Views
Registered: ‎07-23-2019

Re: Xilinx & Vivado, frustration

Imo, all the guts of AXI blocks tend to change even in consecutive releases, so they have to be individually checked every time. I'm currently using 2019.1 for a project, have some project from a third party done with 2018.2 and their source crashes with my release (a customized FSBL for Zynq ultrascale) so I'm planning to wipe this release and move backwards. Yes, it's a PITA, I know. Some people prefer to stick to a specific release for a long time and only upgrade the tools every two years or so. Even keep the same tool release for all the project life. There is a cost and risk in "upgrading" the tools. It's not always as flowery as the "click here and get the latest blah blah". Let's call it the "black side of upgrading they'll never tell you about..."

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354 Views
Registered: ‎08-28-2019

Re: Xilinx & Vivado, frustration

Thank you, are they're any guides or tutorials for some one like me who is ignorant on Vivado usage ?

Kind Regards,
Sy
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334 Views
Registered: ‎07-23-2019

Re: Xilinx & Vivado, frustration

The Xilinx DocNav (installs with vivado) is probably the easiest, most complete and updated source of documents. Probably too many. It's our times, from information to too much information. What was 'finding' now is 'sieving'.

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276 Views
Registered: ‎08-28-2019

Re: Xilinx & Vivado, frustration

Today in another attempt to move forward and resolve the problem...

  1. Launched Vivado 2019.1
  2. Clicked on File > Project > Open...
  3. Navigated to the exisitng 2016.2 project (C:/Users/u49100/AppData/Local/Programs/Git/Zybo/Zybo-project/CARE-0001/proj_hsorter.xpr) and clicked on the OK button.
  4. After opening a dialog is displayed with title "Project is Read-Only", clicked on "Save Project As..." button.
  5. Specified folder (C:\Users\u49100\AppData\Local\Programs\Git\Zybo\Zybo-project\CARE-0001 2019.1) and clicked the "Select" button.
  6. Entered "proj_hsorter" into "Project name" text box and clicked the "OK" button.

After doing there is a progress dialog, then a "Project Upgraded" dialog.  This shows the content:

        Your project uses Xilinix IP. Some of these IP may have undergone changes in
        this release of the software. To see the recommended actions, use the Report
        IP Status button.
        This report can be accessed at any time using the Reports -> Report IP Status
        menu item.
        If using remote IP, you may with to create a backup copy of the IP and the
        output products prior to upgrading the IP to the current release.

I clicked o the "Report IP Status" button.  Another dialog is displayed with title "Report IP Status"

The design contains IP with major version changes.  Please refer to the Change Log
to understand the impact of upgrading an IP with major version change in your design,
prior to upgrading.

I clicked the "Ok" button.  Looking at the "IP Status" log I see the following:

design_hsorter, under this there are 6 entries listed:

/clk_wiz_0                                                                , IP major version change, Upgrade IP, (2019.1, Version 6.0 (Rev.3) Bug FixL Internal GUI fixes, Other: New family support added).

/rst_processing_system7_0_100M                           , IP revision change        , Upgrade IP, (2019.1, Version 5.0 (Rev.13), No changes)

/processing_system7_0_axi_periph                         , IP revision change        , IP 'design_hsorter_processing_system7_0_axi_periph_0' recommendations(s): Target IP definition 'AXI Interconnect (2.1)' requires a revision change. Please review the change log before upgrading the IP.

/processing_system7_0                                             , IP revision change       , 2019.1: Version 5.5 (Rev. 6), No changes

/MEMORY_MAP_HYPERSPECTRAL_2016_2_1, Up-to-date                   , No changes required

/HYPERSPECTRAL_IFB_TOP_0                          , Up-to-date                   , No changes required

I've tried clicking the "Upgrade IP" links, nothing happens or changes. 

Kind Regards,
Sy
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