Xilkernel BSP + LWIP in Socket mode compilation failure with vivado 2014.2 SDK (VC707 hardware)

[sriharsha96]

Hi Everyone,

I am trying to run Xilkernel BSP with LWIP socket on VC707 Virtex 7 target hardware.

AXI_Etherent and AXI_FIFO are used as part of Ethernet logic connected to Microblaze. Our software requirement is to use Xilkernel BSP with LWIP stack in Socket mode. 

I am facing with compilation errors when the Xilkernel is built with LWIP stack in Socket mode. This issue is persistent with Vivado 2014.2 SDK and searching in the xilinx forum, I obtained the answer AR#61178 (http://www.xilinx.com/support/answers/61178.html). Following the steps from that patch resolves the compilation issue, but hangs the Microblaze application execution on VC707 target hardware when run from SDK debug session. 

Without the patch for Vivado 2014.2 software, we are not able to compile the Xilkernel with LWIP stack in Socket mode. With the patch applied to Vivado 2014.2, the application execution hangs in SDK debug session. 

Further suggestions to resolve the issue will be much appreciated. Thanks

[mainvoid]

Hi,

Make sure your pthread stack size is at least 0x8000 (32768 bytes).

This is what lwip code needs for it's tcp threads however default Xilkernel value is 0x1000.

You can change this value in BSP settings: Overview->xilkernel->config_pthread_mutex->pthread_stack_size.

Otherwise in my case lwip silently kept spinning in lwip_init unable to create tcp thread.

Hope this helps.

[sriharsha96]

Hi mainvoid, 

I have tried increasing the pthread stack size. No help.

Are you using Vivado 2014.2 SDK? Have you applied the patches suggested in the link http://www.xilinx.com/support/answers/61178.html?

After applying the patch, even the simple hello world sample project is hanging on VC707 hardware while running from 2014.2 SDK debug session. Once the debug session is started, the control never reaches to microblaze application to perform single step.

Regards

Harsha

[mainvoid]

Right,

Can you check out one more thing then.

Look in your /xilkernel_bsp_0/your_hw_platform/libsrc/xilkernel_v6_1/src/include/os_config.h

Can you see there this line:

#define N_INIT_SELF_PTHREADS 1

Tell me if the line is there.

Cheers.

[sriharsha96]

Hi,

Yeah, the line #define N_INIT_SELF_PTHREADS 1 is present in the file os_config.h. 

Regards,

Harsha

[mainvoid · Accepted solution]

Hi Harsha,

After patching SDK against lwip build error I also get this line which causes system crash.

As a workaround you can try the following:

Open the following file (depends on location on your system obviously):

C:\Xilinx\SDK\2014.2\data\embeddedsw\lib\bsp\xilkernel_v6_1\data\xilkernel.tcl

Find the following line:

set n_init_self_pthreads [llength [get_arrays $static_pthread_table_handle -of_objects $os_handle]]

(line 356 in my file).

Replace it with

set n_init_self_pthreads ""

Regenerate BSP sources, rebuild your app and run it.

Let me know if it worked for you.

Cheers

[sriharsha96]

Hi,

I have updated the xilkernel.tcl file with the suggestion you made. I am able to execute the sample application on the VC707 hardware in SDK debug session. 

Thank you very much for the help.

Regards,

Harsha

[kmshaw_saic]

Hi Harsha,

I also have created a Microblaze LWIP design in Socket mode for the VC707. Everything compiles and runs, but I get an "axidma_send_handler: Error: axidma error interrupt is asserted" message after the link is established. Did you run into a similar problem? If I leave the Ethernet cable disconnected from the VC707, I don't get the message. As soon as I plug it in, LWIP prints the connect message and then I immediately get the DMA error.

My design is based off of the VC707 BIST design. Did you use that as a starting point or did you create your own?

Thanks,

Kevin

[sriharsha96]

Hi Kevin,

I handle only software part of the design. My team mate has provided the FPGA design. I have not come across such error during testing.

We have tested Ethernet interface on VC707 hardware with two set of FPGA designs. One with the default BIST bit file which is based on AXI_Ethernet and AXI_DMA. Second one is based on AXI_Ethernet with AXI_FIFO designed by our team. Both designs were successfully tested on VC707 hardware.

I guess, I am not much of help for you in terms of rectifying FPGA design issues. Enable netif, lwip, sys debug functionality in LWIP settings during xilkernel compilation. Observe any of the steps in dma init is failing during ethernet initialization. 

Have you modified the BIST design or tested on the prebuilt BIST bit file from the project? Its good to test it on prebuilt bit file just to make sure the LWIP settings working fine.

Regards,

Harsha