UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor debosteebo
Visitor
1,639 Views
Registered: ‎04-12-2012

Xilkernel Lwip Issues after initializing large number of semaphores (118)

I would like to know if anyone has experienced or have recommendations on how to debug the following issue with Xilkernel + LWIP + ML605.

 

 

When implementing in Xilkernel, I hit a consistent issue where LWIP's accept and/or select routines will start to crash when after approximately 118 semaphores have been ininitialized.  I have verified my Xilkernel BSP settings that I am familiar with are set correctly to set this number of semaphores (config_sema max_sem=130, max_sem_waitq=130).  Furthermore, altering the runtime heap and stack sizes does not appear to play a role as increasing/decreasing these sizes doesnt change the consistency of the issue.  I have gone to the point where I have essentially commented out all my code execept for a single thread which initializes 118 semaphores and basic lwip routines.  There are two flavors of of lwip crash observations.  One is that lwip_select will immediately unblock with "timeout" even if set to "forever block" or a set number block.  The other observation is that lwip_accept will return a negative descriptor upon client connection with no errno indication.  Just to reiterate, note that these issues are nonexistent if there are "117" or less semaphores related.  Any idea of what I should check next?

 

 


 PARAMETER VERSION = 2.2.0


BEGIN OS
 PARAMETER OS_NAME = xilkernel
 PARAMETER OS_VER = 5.01.a
 PARAMETER PROC_INSTANCE = mb
 PARAMETER STDIN = Console_Uart
 PARAMETER STDOUT = Console_Uart
 PARAMETER SYSTMR_SPEC = true
 PARAMETER SYSTMR_DEV = timer
 PARAMETER SYSINTC_SPEC = int_ctl
 PARAMETER CONFIG_SEMA = true
 PARAMETER CONFIG_MSGQ = true
 PARAMETER USE_MALLOC = true
 PARAMETER MAX_PTHREADS = 25
 PARAMETER PTHREAD_STACK_SIZE = 32768
 PARAMETER CONFIG_PTHREAD_MUTEX = true
 PARAMETER MAX_PTHREAD_MUTEX = 50
 PARAMETER MAX_PTHREAD_MUTEX_WAITQ = 20
 PARAMETER MAX_SEM = 130
 PARAMETER MAX_SEM_WAITQ = 130
 PARAMETER CONFIG_TIME = true
 PARAMETER MAX_READYQ = 20
 PARAMETER MAX_TMRS = 50
 PARAMETER ENHANCED_FEATURES = true
 PARAMETER CONFIG_YIELD = true
 PARAMETER NUM_MSGQS = 30
 PARAMETER STATIC_PTHREAD_TABLE = ((main_thread,1))
END


BEGIN PROCESSOR
 PARAMETER DRIVER_NAME = cpu
 PARAMETER DRIVER_VER = 1.13.a
 PARAMETER HW_INSTANCE = mb
END


BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = Console_Uart
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = v6_ddrx
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = DDR3_SDRAM
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 3.00.a
 PARAMETER HW_INSTANCE = DIP_Switches_8Bits
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = axiethernet
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = ETHERNET
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = axidma
 PARAMETER DRIVER_VER = 5.00.a
 PARAMETER HW_INSTANCE = ETHERNET_dma
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 3.00.a
 PARAMETER HW_INSTANCE = FMC_GPIO
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 3.00.a
 PARAMETER HW_INSTANCE = HSADC_GPIO
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = iic
 PARAMETER DRIVER_VER = 2.04.a
 PARAMETER HW_INSTANCE = IIC_EEPROM
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 3.00.a
 PARAMETER HW_INSTANCE = LEDs_8Bits
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 3.00.a
 PARAMETER HW_INSTANCE = LEDs_Positions
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 3.00.a
 PARAMETER HW_INSTANCE = Push_Buttons_5Bits
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = spi
 PARAMETER DRIVER_VER = 3.03.a
 PARAMETER HW_INSTANCE = SPI_HS_ADCS
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = spi
 PARAMETER DRIVER_VER = 3.03.a
 PARAMETER HW_INSTANCE = SPI_RX_A
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = spi
 PARAMETER DRIVER_VER = 3.03.a
 PARAMETER HW_INSTANCE = SPI_RX_B
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = clk_tst_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = debug_module
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = intc
 PARAMETER DRIVER_VER = 2.03.a
 PARAMETER HW_INSTANCE = int_ctl
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 3.00.a
 PARAMETER HW_INSTANCE = mb_d_bram_ctrl
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 3.00.a
 PARAMETER HW_INSTANCE = mb_i_bram_ctrl
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = sigconx_if_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = tmrctr
 PARAMETER DRIVER_VER = 2.04.a
 PARAMETER HW_INSTANCE = timer
END


BEGIN LIBRARY
 PARAMETER LIBRARY_NAME = lwip140
 PARAMETER LIBRARY_VER = 1.00.a
 PARAMETER PROC_INSTANCE = mb
 PARAMETER API_MODE = SOCKET_API
END



_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x40000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x40000;

/* Define Memories in the system */

MEMORY
{
   mb_i_bram_ctrl_mb_d_bram_ctrl : ORIGIN = 0x00000050, LENGTH = 0x0003FFB0
   DDR3_SDRAM_S_AXI_BASEADDR : ORIGIN = 0xA4000000, LENGTH = 0x04000000
}

/* Specify the default entry point to the program */

ENTRY(_start)

/* Define the sections, and where they are mapped in memory */

SECTIONS
{
.vectors.reset 0x00000000 : {
   *(.vectors.reset)
}

.vectors.sw_exception 0x00000008 : {
   *(.vectors.sw_exception)
}

.vectors.interrupt 0x00000010 : {
   *(.vectors.interrupt)
}

.vectors.hw_exception 0x00000020 : {
   *(.vectors.hw_exception)
}

.text : {
   *(.text)
   *(.text.*)
   *(.gnu.linkonce.t.*)
} > DDR3_SDRAM_S_AXI_BASEADDR

.init : {
   KEEP (*(.init))
} > DDR3_SDRAM_S_AXI_BASEADDR

.fini : {
   KEEP (*(.fini))
} > DDR3_SDRAM_S_AXI_BASEADDR

.ctors : {
   __CTOR_LIST__ = .;
   ___CTORS_LIST___ = .;
   KEEP (*crtbegin.o(.ctors))
   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
   KEEP (*(SORT(.ctors.*)))
   KEEP (*(.ctors))
   __CTOR_END__ = .;
   ___CTORS_END___ = .;
} > DDR3_SDRAM_S_AXI_BASEADDR

.dtors : {
   __DTOR_LIST__ = .;
   ___DTORS_LIST___ = .;
   KEEP (*crtbegin.o(.dtors))
   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
   KEEP (*(SORT(.dtors.*)))
   KEEP (*(.dtors))
   __DTOR_END__ = .;
   ___DTORS_END___ = .;
} > DDR3_SDRAM_S_AXI_BASEADDR

.rodata : {
   __rodata_start = .;
   *(.rodata)
   *(.rodata.*)
   *(.gnu.linkonce.r.*)
   __rodata_end = .;
} > DDR3_SDRAM_S_AXI_BASEADDR

.sdata2 : {
   . = ALIGN(8);
   __sdata2_start = .;
   *(.sdata2)
   *(.sdata2.*)
   *(.gnu.linkonce.s2.*)
   . = ALIGN(8);
   __sdata2_end = .;
} > DDR3_SDRAM_S_AXI_BASEADDR

.sbss2 : {
   __sbss2_start = .;
   *(.sbss2)
   *(.sbss2.*)
   *(.gnu.linkonce.sb2.*)
   __sbss2_end = .;
} > DDR3_SDRAM_S_AXI_BASEADDR

.data : {
   . = ALIGN(4);
   __data_start = .;
   *(.data)
   *(.data.*)
   *(.gnu.linkonce.d.*)
   __data_end = .;
} > DDR3_SDRAM_S_AXI_BASEADDR

.got : {
   *(.got)
} > DDR3_SDRAM_S_AXI_BASEADDR

.got1 : {
   *(.got1)
} > DDR3_SDRAM_S_AXI_BASEADDR

.got2 : {
   *(.got2)
} > DDR3_SDRAM_S_AXI_BASEADDR

.eh_frame : {
   *(.eh_frame)
} > DDR3_SDRAM_S_AXI_BASEADDR

.jcr : {
   *(.jcr)
} > DDR3_SDRAM_S_AXI_BASEADDR

.gcc_except_table : {
   *(.gcc_except_table)
} > DDR3_SDRAM_S_AXI_BASEADDR

.sdata : {
   . = ALIGN(8);
   __sdata_start = .;
   *(.sdata)
   *(.sdata.*)
   *(.gnu.linkonce.s.*)
   __sdata_end = .;
} > DDR3_SDRAM_S_AXI_BASEADDR

.sbss : {
   . = ALIGN(4);
   __sbss_start = .;
   *(.sbss)
   *(.sbss.*)
   *(.gnu.linkonce.sb.*)
   . = ALIGN(8);
   __sbss_end = .;
} > DDR3_SDRAM_S_AXI_BASEADDR

.tdata : {
   __tdata_start = .;
   *(.tdata)
   *(.tdata.*)
   *(.gnu.linkonce.td.*)
   __tdata_end = .;
} > DDR3_SDRAM_S_AXI_BASEADDR

.tbss : {
   __tbss_start = .;
   *(.tbss)
   *(.tbss.*)
   *(.gnu.linkonce.tb.*)
   __tbss_end = .;
} > DDR3_SDRAM_S_AXI_BASEADDR

.bss : {
   . = ALIGN(4);
   __bss_start = .;
   *(.bss)
   *(.bss.*)
   *(.gnu.linkonce.b.*)
   *(COMMON)
   . = ALIGN(4);
   __bss_end = .;
} > DDR3_SDRAM_S_AXI_BASEADDR

_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );

_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );

/* Generate Stack and Heap definitions */

.heap : {
   . = ALIGN(8);
   _heap = .;
   _heap_start = .;
   . += _HEAP_SIZE;
   _heap_end = .;
} > DDR3_SDRAM_S_AXI_BASEADDR

.stack : {
   _stack_end = .;
   . += _STACK_SIZE;
   . = ALIGN(8);
   _stack = .;
   __stack = _stack;
} > DDR3_SDRAM_S_AXI_BASEADDR

_end = .;
}


 

0 Kudos