Zynq UltraScale+ Processing System DDR Burst Length

[smellor]

I get an error when trying to attach the SDK to the target via JTAG. The error is the same as detialed in this Answers Record:

https://www.xilinx.com/support/answers/67623.html

The solution is to use the "Zynq UltraScale+ Processing System GUI" to modify the "PS DDR Burst Length" to be 8 instead of the default of 16. I'm using Vivado 2018.3 and VCU TRD design (rdf0428) on the ZCU106 dev board and I have not been able to find any option to change the DDR burst length.

How can the burst length be changed?

[ritakur]

That setting is removed in the latest version.
Please check the following SODIMM issue for your ZCU106 board. I think you would need to run FSBL first, then run VCU TRD example.
https://www.xilinx.com/support/answers/71961.html

[andrea.douglas@honeywell.com · Accepted solution]

Running FSBL first then my app fixed the problem.