06-21-2019 08:55 AM
I get an error when trying to attach the SDK to the target via JTAG. The error is the same as detialed in this Answers Record:
The solution is to use the "Zynq UltraScale+ Processing System GUI" to modify the "PS DDR Burst Length" to be 8 instead of the default of 16. I'm using Vivado 2018.3 and VCU TRD design (rdf0428) on the ZCU106 dev board and I have not been able to find any option to change the DDR burst length.
How can the burst length be changed?
06-24-2019 07:16 PM