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6,751 Views
Registered: ‎04-06-2010

a problem with clock generator?

I have add an IP attached with microblaze by FSL. But in the clock generator, I can't find the component IP, FSL etc. Can anyone help me?

      Thanks a lot!

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Xilinx Employee
Xilinx Employee
6,729 Views
Registered: ‎08-02-2007

Hi,

 

Plz attach the MHS explaining the problem.

 

Thnx

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6,707 Views
Registered: ‎04-06-2010

 
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Anonymous
Not applicable
6,690 Views

Hi,

 

why do you want to see your FSL instantiation in the clock generator?

what do you mean?

As I could see in your design you have used a DCM in your design which feeds clock of all other modules - clk_100_0000MHz - now I can see that all modules are receiving their clocks from this signal

and also I could see that you have two or three instants of FSL : "fsl_v20"

would you please explain the issue more?

 

tnx,

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6,687 Views
Registered: ‎04-06-2010

Hi,

    I have an IP matrice attached to the processor by FSL. I want to let all of the components to work in different frequencies. So I want to use the clock generator to have multiple frequencies. But in the clock generator, I can't see my IP matrice and my buses matrice_0_to_microblaze_0 and microblaze_0_to_matrice_0.

   In the case, there is already CLKOUT0: clk_100_0000MHz. I want to have CLKOUT1: clk_125_0000MHz etc. for the other components.

   Best wishes!

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Anonymous
Not applicable
6,649 Views

Hi,

 

In your MHS file define another output for your clock_generator
Like this " PORT CLKOUT1 = clk_125_Meg " then save it
And assigne that name for your FSL_CLK and all other PORTS which need
To have the same clock.
Then go to the system assembly view of your project
In EDK and right click on clock_generator and select configure IP.
In system tab view, you can see those clocks which have been
Used by your peripherals.

There you can change the frequency of FSL_CLK
And push "Validate Clocks" then press OK.
EDK will automatically use clkFX of a DCM - mostly DCM0 - for FSL_CLK
You can confirm this by going to the  Low_level Parameters tab of clock generator and see
If it has chnaged the value of C_CLKOUT1_PORT top CLKFX.

I think this may help you.
There's another way that you can use clock generator IP datasheet and
Define some parameters and ports in the MHS file.
The second method may take more time.

Regards,
Hossein Moradi.

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6,637 Views
Registered: ‎04-06-2010

I have changed the mhs file as you talk. But in my EDK,  I can't find the IP like "matrice" neither FSL "microblaze_to_matrice" and "matrice_to_microblaze" in the system tab view of clock_generator.

   Best regards!

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6,631 Views
Registered: ‎04-06-2010

And in my mpd file, the SIGIS = CLK for the clock of my IP.

BEGIN matrice

## Peripheral ports

PORT FSL_CLK = "", DIR=I, SIGIS=Clk, BUS=MFSL:SFSL

 

I don't know why the IP can't be recognized by the system tab view of clock generator!

 

Best regards!

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