05-08-2014 10:48 AM
I'm trying to do a Modelsim behavioural simulation of the xapp1026 files. I only have a vhdl enabled simulator Modelsim 10.2.
The EDK is set for vhdl simulation not verilog.
When I generated the HDL simulation files and then try to run the simulation, I get an error that I don't have a verilog enabled license for Modelsim. I also note that in the created system.do script that compiles the simulation files, the only component using verilog (vlog command vs. vcom) is the axi_interconnect component.
When I look at : \14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_06_a\hdl there is only a verilog subdirectory for the interconnect core? Why no vhdl? Other components have the vhdl file?
Thanks for any replies.
05-08-2014 12:04 PM - edited 05-08-2014 12:05 PM
The core is only provided as Verilog. If you really need VHDL, you could synthesize the core, use netgen, and back-annotate your simulation with the resulting VHDL simulation model (in lieu of the Verilog source).