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Visitor fidellyo
Visitor
9,976 Views
Registered: ‎01-11-2012

axis to video out image shift

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Hi all, i have searched the forum for an answer regarding an image shift, but nothing helped.

Basically, i am designing a simple system, using ise14.7. The system goes as follow:
Vin2axis--> cfa--> axis2vid out in slave mode connected to a Master vtc gen.
I get lock on the incoming stream from an parallel image sensor input.

The issue i see is that the output image is shifted down by few lines and to the right by few pixels.
I can see this due to the axis2vid out lock signal happening late during capture.

-I have tried to reset vidin2axi during vblan when lock
- inhibit ready pins from the upstream ip(vidwaxis and cfa). Until lock occur
- inhibit valid pins from up stream ip as well before video lock
- added avtc det. And latched intc-if(8) signal to axi-en.

Nothing worked. Either i would get lock but image shift, no lock or lock pins is toggling. Or no lock at all.

How am i supposed to control the video stream to initialise and dump previous data once lock occur?
I have been trying for several days now.

Any ideas/suggestions are very much appreciated.
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Visitor fidellyo
Visitor
18,522 Views
Registered: ‎01-11-2012

Re: axis to video out image shift

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Update:

In case that other people that might have the same issue, I have resolved it by regenerating Hblank signals at the video output port from Hsync and DE signals. 

 

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Xilinx Employee
Xilinx Employee
9,920 Views
Registered: ‎08-02-2011

Re: axis to video out image shift

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Hello,

 

I don't think the exact point when the locked signal goes high relative to the input stream is particularly interesting.

 

I'd pay more attention to the data relative to the timing signals and see if it matches on the AXIS input interface and the video output interface. I.e. set up an ILA to trigger on TUSER and capture a couple lines with a test pattern. Then do the same on falling edge of vsync output. From there, you can start to draw some meaningful conclusions.

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Visitor fidellyo
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9,913 Views
Registered: ‎01-11-2012

Re: axis to video out image shift

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Hi bwiec, thank you so much for the prompt reply (on a weekend, Sunday morning!). Very impressed.

good to know that the lock signal is not as important as i thought. 

To remove any other potential issues from reset (i saw few posts talking about it), I have had sequenced them by HW, asserted from downstream IP to upstream (video in) and de-asserted in the same order. 

 

instead of using TPG (either TPG IP or image sensor TPG), i have used a line counter as data in so i can see where things are hapeneing w.r.t. to the SOF. 

 

you can see from the attached captures, the shift happening from top to bottom and few pixels to the right (at least that's what i think).

the video out (RGB30) data(0) looks ok except the one pixel at the begining of the SOF (on the CFA side). 

 

BTW, this issue is hapening with and without the CFA in the design.

I was thinking the issue would be with the embedded FIFO not flushing out data when SOF is happening, hence the 4 lines + few pixels mismatch.

 

thanks again for the support.

 

cfa_sof1.png
cfa_sof2.png
VidOut_vsync.png
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Visitor fidellyo
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9,907 Views
Registered: ‎01-11-2012

Re: axis to video out image shift

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bwiec, just for completness, i have reconfigured the design with vidOut data added to Chipscope.

 

cfa_sof3_withDataOutbusAdded.png
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Visitor fidellyo
Visitor
9,901 Views
Registered: ‎01-11-2012

Re: axis to video out image shift

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I have reconfigured with the image sensor TPG so we can start from a known base ground (attached).

 

note the following configuration of various blocks:

- VidIn as 10 bits raw pixel, output is 16 bits

- CFA input as 16 bits, and output is 32 bits

- VidOut input as 32 bits and output as 30bits.

i am trimming the LSB's after the VidOut IP data output to get RGB565 (a crude way of conversion a.t.m since it's a hardware output limitation)

TestPatternOutput_FPGAvsImageSensorDS_vsyncout.png
TestPatternOutput_FPGAvsImageSensorDS_SOF.png
TestPatternOutput_FPGAvsImageSensorDS.png
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Re: axis to video out image shift

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Sure, happy to help!

 

Hmm, I'm going to have to stare at these for a little while.

 

The one interesting thing is that vtc_ce is not toggling at all. Presumably you have the core in slave mode, right? Do you ever see this toggling (i.e. before lock)?

 

Do you notice any correlation of the amount of shift with the FIFO depth setting?

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Visitor fidellyo
Visitor
9,853 Views
Registered: ‎01-11-2012

Re: axis to video out image shift

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Bwiec, i see vtc_ce toggling at the beginning, before lock. 

you are correct, i am running in slave mode.

FIFO depth has no correlation with the number of line shift (i have thought about it and used many depth size to confirm).

 

as of note, i am running all of the cores at input pixel clock rate. i have noticed, in VTC (detect mode), it looses detection (intc_if(8) toggles) when hblank is not toggling during vblank coming from the sensor. do you think this might be an issue? 

 

 

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Visitor fidellyo
Visitor
9,792 Views
Registered: ‎01-11-2012

Re: axis to video out image shift

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update:

i have replaced Vin2AXIS by an internal TPG (TPG-VTC-AXIS2Vout), it does not seem to have an image shift. (if other people wondering, AXIS2Vout changed to master and VTC-CE was tied to always high).

 

put back Vin2AXIS IP, and removed CFA IP (Vin2AXIS-VTC-AXIS2Vout, AXIS2Vout in slave mode), the image shift is back again.

so, it seems that the issue appears when Vin2AXIS (or the image sensor) is connected to the system. 

 

i have checked SOF and EOL Vin and Vout data, which seems to be the same value.

 

any thoughts/ideas? 

Vin2VoutSOFvalues-VinVTCVout.png
Vin2VoutEOLvalues-VinVTCVout.png
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Visitor fidellyo
Visitor
18,523 Views
Registered: ‎01-11-2012

Re: axis to video out image shift

Jump to solution

Update:

In case that other people that might have the same issue, I have resolved it by regenerating Hblank signals at the video output port from Hsync and DE signals. 

 

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