I would like to create a a "black box" in between cache and the external memory controller. The project I have is to basically add some security to cached data and instructions before they are written/read to/from the external memory.
So the current issues are
1. Finding a good reference describing the interface between the cache and the memory controller. E.g. looking for signal definitions, timing diagrams etc.
2. Using the EDK to implement this. It seems the create IP wizard restricts you to other types of buses such as FSL, OPB, LMB etc.
I would like to implement this using the EDK 9.1, the MicroBlaze processor on a Virtex II Pro Board.