We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Observer wen119at
Registered: ‎02-16-2010

clock problem when using EDK in ISE

Hi everyone,


I am using EDK under ISE environment, but got some problems...

My design includes a toplevel(system_top), and a EDK platform(system_i).

There are three different clocks in the design.

Two are the input clock from an camera and are connect to A10 and G33 pin, respectively. The camera is connect to ML605 via FMC module.

The third one is the system clock (Clock_200M) which is directly connect to J9 pin.

When running the XST and implementation, no error occurs.

But when running the BIT file and see from the ChipScope, the two camera clocks remains HIGH.

And I found in the translate message that the tow constraints for the clocks are removed for some reason. See blow:




fmc_imageov_cam1_clk_pin_BUFGP is directly connect to an IP in EDK to provide the clock.

fmc_imageov_video_clk_pin_BUFGP is connected to the clock generator in EDK.

An BUFGP is added to fmc_imageov_cam1_clk_pin_BUFGP.


By the way, IO buffers are added when running XST.


Anyone has idea about this problem? Many thanks.



0 Kudos