UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
6,268 Views
Registered: ‎09-08-2014

configuring the VDMA

I'm trying to configure the VDMA in the SDK. I believe I've implemented the hardware correctly in Vivado 2013.3 and exported to the SDK. However I'm struggling to configure the VDMA.

 

I have got a design that outputs colour bars to the hdmi output. I also have a design that has a camera input and outputs that to the hdmi output. What I want to do is encorporate the VDMA into the this design. What I can't work out is how to configure the VDMA in the SDK.  Have you got any design guide lines that will help me here?  

 

I have the code for initialising the output side as per the colour bar design ie:

 

// Initialize Output Side of AXI VDMA
xil_printf( "Video DMA (Output Side) Initialization ...\n\r" );
vfb_common_init(
pDemo->uDeviceId_VDMA_HdmiDisplay, // uDeviceId
&(pDemo->vdma_hdmi) // pAxiVdma
);

xil_printf( "vfb_tx_init ...\n\r" );

vfb_tx_init(
&(pDemo->vdma_hdmi), // pAxiVdma
&(pDemo->vdmacfg_hdmi_read), // pReadCfg
pDemo->hdmio_resolution, // uVideoResolution
pDemo->hdmio_resolution, // uStorageResolution
pDemo->uBaseAddr_MEM_HdmiDisplay, // uMemAddr
pDemo->uNumFrames_HdmiDisplay // uNumFrames
);

 

What I need is the code for inintialising the input side?

0 Kudos
4 Replies
Explorer
Explorer
6,243 Views
Registered: ‎09-08-2014

Re: configuring the VDMA

Better still would be some information on debugging the IP. I can see it has debug but there is no infrmation on it that I can find ie:

 

#define XPAR_AXI_VDMA_0_ENABLE_DEBUG_INFO_1 0
#define XPAR_AXI_VDMA_0_ENABLE_DEBUG_INFO_5 0
#define XPAR_AXI_VDMA_0_ENABLE_DEBUG_INFO_6 0
#define XPAR_AXI_VDMA_0_ENABLE_DEBUG_INFO_7 0
#define XPAR_AXI_VDMA_0_ENABLE_DEBUG_INFO_9 0
#define XPAR_AXI_VDMA_0_ENABLE_DEBUG_INFO_13 0
#define XPAR_AXI_VDMA_0_ENABLE_DEBUG_INFO_14 0
#define XPAR_AXI_VDMA_0_ENABLE_DEBUG_INFO_15 0
#define XPAR_AXI_VDMA_0_ENABLE_DEBUG_ALL 1

0 Kudos
Xilinx Employee
Xilinx Employee
6,231 Views
Registered: ‎08-02-2011

Re: configuring the VDMA

0 Kudos
Explorer
Explorer
6,221 Views
Registered: ‎09-08-2014

Re: configuring the VDMA

Thanks for the reply. I have looked at all the designs. THe AXI VDMA reference design is helpful but its it intended for a Microblaze processor design. I'm using a Zedboard with a Zynq Cortex A9 processor. So I could implement the design but not run it unless I modify it. I have read thro the document which is helpful. What I may try to do is a Zynq version of this design. However this isn't what I'm trying to achieve long term.

0 Kudos
Xilinx Employee
Xilinx Employee
6,199 Views
Registered: ‎08-02-2011

Re: configuring the VDMA

Hey,

Well the reason I recommended those docs is because the VDMA setup should be very similar, if not identical. Even though the designs may use microblaze, the application software should port without any effort (the tools build the drivers/bsp for you, so it should be trivial). Anyway, the FMC IMAGEON design does target zedboard.

www.xilinx.com
0 Kudos