constraining Clock crossing between an AXI-Slave and AXI strem interfaces
I'm developing a peripheral thats is going to have an XI-Lite inteface to receive some a parameters and an axistream interface(-->Slave-->Master-->) thats is goint to store and receive son data fro RAM. Of course the AXI-Lite interface use a much lower frecuency than the stream one. The aprameters wont change during the processing, I don't think I'll have metastability error because of this. Sso I would like to know how to make the constrains for this perifheral in an ISE/XPS flow.