04-08-2009 04:50 AM - edited 04-08-2009 04:51 AM
I want to build an I/O peripherial that communicate with PPC via Asynch. FIFO module. So i suggest to use FSL which has internally FIFO memory. In addiation i need the PPC to be the slave side, because it will receive the data from FIFO and won't send any data to my IO. But i can't do this using create peripheral wizard because it supports only master mode(i.e. make PPC to be the MASTER), or both master and slave in the same time. and doesn't support only slave mode.
So what is your suggestion to solve this problem.
Note: The Master side will be outside the board (another board). so i need to connect this bus to external IO bin.
Thank you in advanced.
04-08-2009 10:25 PM
If you want to get two processors to communicate on different boards then FSL might not be the best solution. I only say this because you will need to get all the signals across to the other board. Signal integrity at the FSL bus speeds over say 0.5meters may be a huge issue here.
I would try something as simple as RS232, or make a custom IP core with a PLB interface and a SERDES component.
Can anyone else verify, but I don't think FSL was intended for this purpose?
04-09-2009 01:33 AM
this won't be processor to a processor communication.
Just, it seem like one way data transfer without in ACK or handshaking. (It seem like sensor.) so the Asy. FIFO is the best solution.
and FSL contain a bulit in Asynch. FIFO.