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rajuponnaganti
Voyager
Voyager
9,030 Views
Registered: ‎03-12-2015

problem with custom ip

i cteated and packaged ip called myip_asser2 in s-axi_in slave mode.

i added following code c <= a +b;(31 downto 0) for signals a,c and b.

a is assigned to slv_reg_0,b is to slv_reg_1 and c -s to slv-reg_2.

in sdk , my code is 

 

u32 data_1;

Xil_Out32(XPAR_MYIP_ADDER_V2_0_S00_AXI_BASEADDR, 0x00001234);
Xil_Out32(XPAR_MYIP_ADDER_V2_0_S00_AXI_BASEADDR+4, 0xabcd1234);

data_1 = Xil_In32(XPAR_MYIP_ADDER_V2_0_S00_AXI_BASEADDR+8);
xil_printf("added value: %x\n\r",data_1);

 i didnt get output;

 

 

i am getting output is 0;

 

need solution.

i dont know why it is giving out put.

 

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8 Replies
pvenugo
Moderator
Moderator
8,840 Views
Registered: ‎07-31-2012

Hi,

 

Try using 

Xil_Out32(XPAR_MYIP_ADDER_V2_0_S00_AXI_BASEADDR+4, 0x00001234);
Xil_Out32(XPAR_MYIP_ADDER_V2_0_S00_AXI_BASEADDR+8, 0xabcd1234)

 

Regards

Praveen

 

 


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pvenugo
Moderator
Moderator
8,839 Views
Registered: ‎07-31-2012

Also, if possible pls share ur desing and SDK workspace.

 

Regards

Praveen


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rajuponnaganti
Voyager
Voyager
8,812 Views
Registered: ‎03-12-2015

 i am attaching sdk file as zip.try to solve.

we are using vc707 board.

waiting for solution.

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rajuponnaganti
Voyager
Voyager
8,800 Views
Registered: ‎03-12-2015

have you check this?
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rajuponnaganti
Voyager
Voyager
8,762 Views
Registered: ‎03-12-2015

what is the solution?
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signature20
Newbie
Newbie
2,265 Views
Registered: ‎02-19-2018

Hello,

 

Did you get any solution for this issue ?

I am facing a similar problem with Vivado 2017.4

 

Thanks,

Shreya

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rajuponnaganti
Voyager
Voyager
2,254 Views
Registered: ‎03-12-2015

Yes

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signature20
Newbie
Newbie
1,779 Views
Registered: ‎02-19-2018

what is it?

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