04-13-2010 07:07 AM
i need use bram and bram controller in my project to store the output of fft.
can any one tell how to use bram means how to use signal of bram ( din,dout,rnw,en) in user_logic module to write the data into the memory.
it will be very usefull if anyone replies.
04-13-2010 11:47 AM
what tools you using.
if you need a BRAM controler, that implies that you are using EDK.
If you using ISE, then you don't need a BRAM controler, just infer the RAM you require.
This is taken from the Xilinx template file built into ISE.
entity rams_04 is
port (CLK : in std_logic;
WE : in std_logic;
A : in std_logic_vector(5 downto 0);
DI : in std_logic_vector(15 downto 0);
DO : out std_logic_vector(15 downto 0));
architecture syn of rams_04 is
type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0);
signal RAM : ram_type;
if (CLK'event and CLK = '1') then
if (WE = '1') then
RAM(conv_integer(A)) <= DI;
DO <= RAM(conv_integer(A));
04-14-2010 04:59 AM
hi thank u very much for reply. but i m using edk, previously i used fifo to store the output in user_logic module of the custom ip but its not working properly. so i m planning use BRAM and xps_bram controler to store the output.but i dont no how to use the signals regarding memory in user_logic module.
please can u tell if u have some example code to write the output to memory.
04-14-2010 09:21 AM
my memory of EDK and BRAM.
You don't have to wire up anything.
in the EDK, the BRAM controler is instantiated, along with the BRAM and wired up.
BRAM controler is only used for the Processor bus,
04-14-2010 08:28 PM
hi sorry i didnt understand.
i have instantiated my vhdl module in user_logic module. the following like this
generic map (width=>width)
port map(sys_clk=> Bus2IP_Clk,
so i want to store the output eff_addr_temp.(eff_addr_temp is signal) i want to see the output in terminal)
i hope u understand my problem. can u help me please.
i attached my user_logic here(i used fifo to store the output but its not working)
04-14-2010 11:12 PM
well I'm confused,
If your using EDK, then you do not instantiate the BRAM controler, it's done in EDK.
If your doing your own VHDL that does not connect to the Porcessor bus, then that is not in EDK, and you don't need the BRAM controler.
04-15-2010 01:18 PM
Your in EDK.
and you have imported your own peripheral ?
If you just need BRAM, why ?
I'd have just instantiated a BRAM and controler fomr the Xilxin EDK tool directly, and it would have been wired in automaticaly to the PBL bus,
I get impresison you need to take step back, try re doing the EDK tutorial that clomes with Xilinx,
04-16-2010 03:24 AM
hi i need one more clarification.
Is BRAM used only to store a software application (c program or input data from c program) or can it be used to store the output of any user defined peripheral.
eg, can i store the output of the instantiated VHDL program in user_logic module.
04-16-2010 08:48 AM
which bus are you conecting the BRAM too ?
Which bus is your user logic conencting too ?
EDK is Bus based design.
04-17-2010 02:15 AM
sorry all I can say is I'm confused,
not much help I know, but sorry.
04-20-2010 06:11 PM
In my design, BRAM is used to save some data that need deterministic access (comparing with DDR/DDR2 through MPMC -- the access time is not fixed, depending on the other ports are accessing or not). To use BRAM in EDK is straight forward. EDK provide BRAM with two port (A and B). PortA can be used for cpu access. PortB can be used for user logic to read/write user data. Since PortA is used for cpu access, it needs a bram controller (which connects to PortA in one side and PLB in the other side). Hope this helps.