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halas86
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Registered: ‎03-31-2010

spartan 3 xc3s200 dont support plb bus can use the opb bus to my own ip ?

i read in many tutorial that i can add my own ip in to microblaze by usin the plb bus but i tried it in board and an error occur and show that plb is not supported by the board. if its possible to use obp bus to link my ip give me the steps or doc. i need this information for my project to be functionnal or i ll be in problem. any help and ill be grateful.. thx N.B : my ip is a vhdl file and must be add with user_logic.vhd and ip.vhd
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htsvn
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Hi,

 

What is the version of EDK you are using?

 

Thnx

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halas86
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i use the version 8.1i . this is what i done to implement the ip with microblaze using opb : ------------------------------------------------------------------------------ -- user_logic.vhd - entity/architecture pair ------------------------------------------------------------------------------ -- -- *************************************************************************** -- ** Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** Xilinx, Inc. ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** -- ** FOR A PARTICULAR PURPOSE. ** -- ** ** -- *************************************************************************** -- ------------------------------------------------------------------------------ -- Filename: user_logic.vhd -- Version: 1.00.a -- Description: User logic. -- Date: Tue Jun 08 17:39:58 2010 (by Create and Import Peripheral Wizard) -- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- device pins: "*_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "I_<#|FUNC>" ------------------------------------------------------------------------------ -- DO NOT EDIT BELOW THIS LINE -------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v2_00_a; use proc_common_v2_00_a.proc_common_pkg.all; -- DO NOT EDIT ABOVE THIS LINE -------------------- --USER libraries added here ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_DWIDTH -- User logic data bus width -- C_NUM_CE -- User logic chip enable bus width -- -- Definition of Ports: -- Bus2IP_Clk -- Bus to IP clock -- Bus2IP_Reset -- Bus to IP reset -- Bus2IP_Data -- Bus to IP data bus for user logic -- Bus2IP_BE -- Bus to IP byte enables for user logic -- Bus2IP_RdCE -- Bus to IP read chip enable for user logic -- Bus2IP_WrCE -- Bus to IP write chip enable for user logic -- IP2Bus_Data -- IP to Bus data bus for user logic -- IP2Bus_Ack -- IP to Bus acknowledgement -- IP2Bus_Retry -- IP to Bus retry response -- IP2Bus_Error -- IP to Bus error response -- IP2Bus_ToutSup -- IP to Bus timeout suppress ------------------------------------------------------------------------------ entity user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_DWIDTH : integer := 32; C_NUM_CE : integer := 1 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here o_pwm : out std_logic ; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Reset : in std_logic; Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1); Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1); Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1); Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1); IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1); IP2Bus_Ack : out std_logic; IP2Bus_Retry : out std_logic; IP2Bus_Error : out std_logic; IP2Bus_ToutSup : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); end entity user_logic; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of user_logic is --USER signal declarations added here, as needed for user logic signal N :std_logic_vector(0 to C_DWIDTH-1) ; signal Q :std_logic_vector(7 downto 0):= "00000000" ; signal pre_pwm :std_logic ; signal clk :std_logic ; signal pre_clk :std_logic ; signal cmp :std_logic_vector(15 downto 0):="0000000000000000"; ------------------------------------------ -- Signals for user logic slave model s/w accessible register example ------------------------------------------ signal slv_reg0 : std_logic_vector(0 to C_DWIDTH-1); signal slv_reg_write_select : std_logic_vector(0 to 0); signal slv_reg_read_select : std_logic_vector(0 to 0); signal slv_ip2bus_data : std_logic_vector(0 to C_DWIDTH-1); signal slv_read_ack : std_logic; signal slv_write_ack : std_logic; begin --USER logic implementation added here p1: process( Bus2IP_Clk ) begin if (Bus2IP_Clk'event and Bus2IP_Clk='1') then cmp<= cmp + 1 ; if cmp=1953 then pre_clk<= not(pre_clk); cmp<= cmp-cmp ; end if; end if ; end process p1; clk<= pre_clk ; p2: process( clk,Bus2IP_Data ) begin if (clk'event and clk='1') then Q <= Q + 1 ; end if; if Bus2IP_WrCE(0)='1' then N <= Bus2IP_Data ; else N <= N ; end if ; if Q < N then pre_pwm <= '1' ; else pre_pwm <= '0' ; end if; end process p2 ; o_pwm <= pre_pwm ; ------------------------------------------ -- Example code to read/write user logic slave model s/w accessible registers -- -- Note: -- The example code presented here is to show you one way of reading/writing -- software accessible registers implemented in the user logic slave model. -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond -- to one software accessible register by the top level template. For example, -- if you have four 32 bit software accessible registers in the user logic, you -- are basically operating on the following memory mapped registers: -- -- Bus2IP_WrCE or Memory Mapped -- Bus2IP_RdCE Register -- "1000" C_BASEADDR + 0x0 -- "0100" C_BASEADDR + 0x4 -- "0010" C_BASEADDR + 0x8 -- "0001" C_BASEADDR + 0xC -- ------------------------------------------ slv_reg_write_select <= Bus2IP_WrCE(0 to 0); slv_reg_read_select <= Bus2IP_RdCE(0 to 0); slv_write_ack <= Bus2IP_WrCE(0); slv_read_ack <= Bus2IP_RdCE(0); -- implement slave model register(s) SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Reset = '1' then slv_reg0 <= (others => '0'); else case slv_reg_write_select is when "1" => for byte_index in 0 to (C_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7); end if; end loop; when others => null; end case; end if; end if; end process SLAVE_REG_WRITE_PROC; -- implement slave model register read mux SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0 ) is begin case slv_reg_read_select is when "1" => slv_ip2bus_data <= slv_reg0; when others => slv_ip2bus_data <= (others => '0'); end case; end process SLAVE_REG_READ_PROC; ------------------------------------------ -- Example code to drive IP to Bus signals ------------------------------------------ IP2Bus_Data <= slv_ip2bus_data; IP2Bus_Ack <= slv_write_ack or slv_read_ack; IP2Bus_Error <= '0'; IP2Bus_Retry <= '0'; IP2Bus_ToutSup <= '0'; end IMP;
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halas86
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Registered: ‎03-31-2010

i am sorry this is not clear,!!! i don t know why. i attached the user logic file with this message if you can help me . i need to update the "signal N" .it is already declared in the file if i fix th value of N i get my pwm_out signal correctly on led. but i like to control the the value of " N "from the software so i write value to register but after that i dont know how to put this value in " N" . an other thing, if i like to use the uartlite to input the value of N how can make it ?? i just find the function to input just one caracter but a a number of 8bit ???? i appreciate your help and i need to get the solution .. thx a lot
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halas86
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halas86
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------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.            **
-- **                                                                       **
-- ** Xilinx, Inc.                                                          **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND       **
-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION           **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,     **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE      **
-- ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY              **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
-- ** FOR A PARTICULAR PURPOSE.                                             **
-- **                                                                       **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename:          user_logic.vhd
-- Version:           1.00.a
-- Description:       User logic.
-- Date:              Tue Jun 08 17:39:58 2010 (by Create and Import Peripheral Wizard)
-- VHDL Standard:     VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
--   active low signals:                    "*_n"
--   clock signals:                         "clk", "clk_div#", "clk_#x"
--   reset signals:                         "rst", "rst_n"
--   generics:                              "C_*"
--   user defined types:                    "*_TYPE"
--   state machine next state:              "*_ns"
--   state machine current state:           "*_cs"
--   combinatorial signals:                 "*_com"
--   pipelined or register delay signals:   "*_d#"
--   counter signals:                       "*cnt*"
--   clock enable signals:                  "*_ce"
--   internal version of output port:       "*_i"
--   device pins:                           "*_pin"
--   ports:                                 "- Names begin with Uppercase"
--   processes:                             "*_PROCESS"
--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------

-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------

--USER libraries added here

------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
--   C_DWIDTH                     -- User logic data bus width
--   C_NUM_CE                     -- User logic chip enable bus width
--
-- Definition of Ports:
--   Bus2IP_Clk                   -- Bus to IP clock
--   Bus2IP_Reset                 -- Bus to IP reset
--   Bus2IP_Data                  -- Bus to IP data bus for user logic
--   Bus2IP_BE                    -- Bus to IP byte enables for user logic
--   Bus2IP_RdCE                  -- Bus to IP read chip enable for user logic
--   Bus2IP_WrCE                  -- Bus to IP write chip enable for user logic
--   IP2Bus_Data                  -- IP to Bus data bus for user logic
--   IP2Bus_Ack                   -- IP to Bus acknowledgement
--   IP2Bus_Retry                 -- IP to Bus retry response
--   IP2Bus_Error                 -- IP to Bus error response
--   IP2Bus_ToutSup               -- IP to Bus timeout suppress
------------------------------------------------------------------------------

entity user_logic is
  generic
  (
    -- ADD USER GENERICS BELOW THIS LINE ---------------
    --USER generics added here
    -- ADD USER GENERICS ABOVE THIS LINE ---------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol parameters, do not add to or delete
    C_DWIDTH                       : integer              := 32;
    C_NUM_CE                       : integer              := 1
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
  port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
    --USER ports added here
    o_pwm                                        : out std_logic ;
    -- ADD USER PORTS ABOVE THIS LINE ------------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol ports, do not add to or delete
    Bus2IP_Clk                     : in  std_logic;
    Bus2IP_Reset                   : in  std_logic;
    Bus2IP_Data                    : in  std_logic_vector(0 to C_DWIDTH-1);
    Bus2IP_BE                      : in  std_logic_vector(0 to C_DWIDTH/8-1);
    Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_CE-1);
    Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_CE-1);
    IP2Bus_Data                    : out std_logic_vector(0 to C_DWIDTH-1);
    IP2Bus_Ack                     : out std_logic;
    IP2Bus_Retry                   : out std_logic;
    IP2Bus_Error                   : out std_logic;
    IP2Bus_ToutSup                 : out std_logic
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
end entity user_logic;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is

  --USER signal declarations added here, as needed for user logic
    signal N            :std_logic_vector(0 to C_DWIDTH-1)                  ;
    signal Q         :std_logic_vector(7 downto 0):= "00000000" ;
    signal pre_pwm :std_logic                                              ;
    signal clk         :std_logic                                              ;
    signal pre_clk    :std_logic                                              ;
    signal cmp         :std_logic_vector(15 downto 0):="0000000000000000";
  ------------------------------------------
  -- Signals for user logic slave model s/w accessible register example
  ------------------------------------------
  signal slv_reg0                       : std_logic_vector(0 to C_DWIDTH-1);
  signal slv_reg_write_select           : std_logic_vector(0 to 0);
  signal slv_reg_read_select            : std_logic_vector(0 to 0);
  signal slv_ip2bus_data                : std_logic_vector(0 to C_DWIDTH-1);
  signal slv_read_ack                   : std_logic;
  signal slv_write_ack                  : std_logic;

begin

  --USER logic implementation added here
    p1: process( Bus2IP_Clk )
    begin
        if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
             cmp<= cmp + 1 ;
            if cmp=1953    then
               pre_clk<= not(pre_clk);
                cmp<= cmp-cmp ;
            end if;
        end if ;
    end process p1;
    clk<= pre_clk ;            
    
    p2: process( clk,Bus2IP_Data )
    begin
        if (clk'event and clk='1')
            then Q <= Q + 1 ;
        end if;
    
    
        if Bus2IP_WrCE(0)='1' then
            N <= Bus2IP_Data ;
        else N <= N ;
        end if ;
        
        if Q < N  
            then pre_pwm <= '1' ;
            else pre_pwm <= '0' ;
        end if;        
    end process p2 ;
    o_pwm <= pre_pwm ;
  ------------------------------------------
  -- Example code to read/write user logic slave model s/w accessible registers
  --
  -- Note:
  -- The example code presented here is to show you one way of reading/writing
  -- software accessible registers implemented in the user logic slave model.
  -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
  -- to one software accessible register by the top level template. For example,
  -- if you have four 32 bit software accessible registers in the user logic, you
  -- are basically operating on the following memory mapped registers:
  --
  --    Bus2IP_WrCE or   Memory Mapped
  --       Bus2IP_RdCE   Register
  --            "1000"   C_BASEADDR + 0x0
  --            "0100"   C_BASEADDR + 0x4
  --            "0010"   C_BASEADDR + 0x8
  --            "0001"   C_BASEADDR + 0xC
  --
  ------------------------------------------
  slv_reg_write_select <= Bus2IP_WrCE(0 to 0);
  slv_reg_read_select  <= Bus2IP_RdCE(0 to 0);
  slv_write_ack        <= Bus2IP_WrCE(0);
  slv_read_ack         <= Bus2IP_RdCE(0);

  -- implement slave model register(s)
  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
  begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' then
        slv_reg0 <= (others => '0');
      else
        case slv_reg_write_select is
          when "1" =>
            for byte_index in 0 to (C_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
          when others => null;
        end case;
      end if;
    end if;

  end process SLAVE_REG_WRITE_PROC;

  -- implement slave model register read mux
  SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0 ) is
  begin

    case slv_reg_read_select is
      when "1" => slv_ip2bus_data <= slv_reg0;
      when others => slv_ip2bus_data <= (others => '0');
    end case;

  end process SLAVE_REG_READ_PROC;
 
 
  ------------------------------------------
  -- Example code to drive IP to Bus signals
  ------------------------------------------
  IP2Bus_Data        <= slv_ip2bus_data;
  IP2Bus_Ack         <= slv_write_ack or slv_read_ack;
  IP2Bus_Error       <= '0';
  IP2Bus_Retry       <= '0';
  IP2Bus_ToutSup     <= '0';

end IMP;

 

and the software file that i tried is ::

#include "xparameters.h"
#include "stdio.h"
#include "xutil.h"
#include "xstatus.h"
#include "xuartlite_l.h"
#include "xuartlite.h"
#include "pwm.h"
#include "xbasic_types.h"
#include "xio.h"
#include "pwm2.h"

 

Xuint32 XPAR_pwm2_0_BASEADDR = 0x71200000 ;
Xuint32 Reg32Value;
int main (void)
{
xil_printf("User logic slave module test...\n\r");
   xil_printf("   - write 20 to slave register 0\n\r");
   PWM2_mWriteReg(XPAR_pwm2_0_BASEADDR, 0,3221225696 );
   Reg32Value = PWM2_mReadReg(XPAR_pwm2_0_BASEADDR, 0);
   xil_printf("   - read %d from register 0\n\r", Reg32Value);
   if ( Reg32Value != (Xuint32) 3221225696)
   {
      xil_printf("   - slave register 0 write/read failed\n\r");
      return XST_FAILURE;
   }
   xil_printf("   - slave register write/read passed\n\n\r");

   return XST_SUCCESS;
}   

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centaur19
Xilinx Employee
Xilinx Employee
5,719 Views
Registered: ‎08-01-2007

halas86,

 

Here are a couple of things I see -

 

1. You are using 8.1i which is very old. You may want to consider moving to a newer version.

2. You can use OPB because Microblaze never had a PLBv34 interface. The idea of creating a custom ip with OPB/PLB is the same. The create/import wizard will help you create the IPIF. Thereafter the process is the same. You can also invoke the docs from the wizard by selecting More Info.

 

You have pasted the User logic. Do you see an error in compilation? Or is it that it doesnt work?

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halas86
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Registered: ‎03-31-2010

first of all thx.

in the zone of user implementation you can a signal named N. i try to write a value in slv_reg0 and then put it in the N in order to change it every time i like.but it seems that the signal N isnt changed by the value in the register. if i fix the Value of N and i import the ip it work but its a command of a servo motor so it must change always.

i try this ::

 

N<= slv_reg0 ; \\ this in the user_logic

and i write to the register with :  ip_mWritereg (baseaddr,0,value) \\ in c program

 

so it did work and i dont get output  because it depend on the value of N witch return nothing!!!!

if its wrong what the way to put a variable in the ip and control it from the software ???

 

 

 

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