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DannyF
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Registered: ‎07-23-2020

stuck in the UG1165 tutorial with ZC702. defining GPIO turn into i,o,t pins instead of a single io like the tutorial.

Hi, i am a complete newby. and i am trying to follow the UG1165 tutorial. i am using the recent tutorial and vivado 2020.1.

i am on page 35 of the tutorial, and instead of getting this : 

tutorial.png

i am getting the GPIO as io, its split into i,o and t.

since they act as inputs that monitor switches, i tried just linking the just the input pins, like so : 

mine.png

 

but i end up with an error saying :

  • [DRC UCIO-1] Unconstrained Logical Port: 4 out of 136 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: GPIO_0_0_tri_t[0], GPIO_0_0_tri_o[0], gpio_sw_tri_t[0], and gpio_sw_tri_o[0].

    i tried looking up a solution, i feel like its a total newby question, but i am stuck. how do i change these 3 pins into a single io pin? please help a newby out

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lettertu
Xilinx Employee
Xilinx Employee
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Registered: ‎06-02-2017

Hi @DannyF 

Did you modify the wrapper file?

Generally, an IOBUF will be instantiated into the wrapper file automatically to convert the three signals to a bi-directional IO.

You can try to re-generate the HDL wrapper or instantiate the IOBUF yourself.

Or if you do like to use it as a input-only signal, you can double-click on the axi_gpio_0 IP and enable "All inputs" option.

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DannyF
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Registered: ‎07-23-2020

i initiated the HDL wrapper automatically, i did not try to change anything myself (mainly cause i dont really know what i am doing at this point)

i did try checking the "all inputs" box in the AXI GPIO, and it did solve it for that GPIO.
however, i didnt manage to do it to the second GPIO which is an external GPIO in the ZYNQ7 processing system block. so the problem wasnt solved completely. 


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DannyF
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Registered: ‎07-23-2020

ok, i figured out how to regenerate the HDL wrapper. there is an IOBUF in there. but being a complete novice i have no idea how to actually turn the 3 ports (i,o,t) into the io port.

it just feels like there's some checkbox not ticked off, and i am stuck right at the start line.

anyways, i attached the generated HDL wrapper. i would appreciate any sort of help.  

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