Hello,
i use the xapp1078 running petalinux on core0 and baremetal on core1, and it works. I changed the design like in the picture. I added a irq_gen1 on addr 0x78700000 which is connected to core1_nFIQ. irq_gen0 on addr 0x78600000 which is still connected to core1_nIRQ.
Therefore, my SetupIntrSystem() routine is the following:
static int SetupIntrSystem( INTC *IntcInstancePtr,
XPlIrq *PeriphInstancePtr,
u16 IntrId,
XPlIrq *PeriphInstancePtr2,
u16 IntrId2)
{
int Status;
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect the interrupt handler that will be called when an
* interrupt occurs for the device.
*/
Status = XScuGic_Connect(IntcInstancePtr, IntrId,
(Xil_ExceptionHandler)PlIntrHandler,
PeriphInstancePtr);
if (Status != XST_SUCCESS) {
xil_printf("ERROR1");
return Status;
}
Status = XScuGic_Connect(IntcInstancePtr, IntrId2,
(Xil_ExceptionHandler)PlIntrHandler2,
PeriphInstancePtr2);
if (Status != XST_SUCCESS) {
xil_printf("ERROR2");
return Status;
}
/*
* Enable the interrupt for the PL device.
*/
XScuGic_Enable(IntcInstancePtr, IntrId);
XScuGic_Enable(IntcInstancePtr, IntrId2);
/*
* Initialize the exception table
*/
Xil_ExceptionInit();
/*
* Register the interrupt controller handler with the exception table
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
IntcInstancePtr);
/*
* Register the interrupt controller handler with the exception table
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_FIQ_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
IntcInstancePtr);
/*
* Enable non-critical exceptions
*/
//Xil_ExceptionEnable();
Xil_ExceptionEnableMask(XIL_EXCEPTION_ALL);
return XST_SUCCESS;
}
when I start this application, i need to set BOTH irq_gen with this command (the order is unimportant):
poke 0x78600000 0x00000001
poke 0x78700000 0x00000001
the ISR of core1_nIRQ will be executed. Never core1_nFIQ! At addr 0x78600000 there is a 0x00000000 and at 0x78700000 still 0x00000001.
what is my problem? i can't find it....
Thanks!
