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Participant
Participant
6,004 Views
Registered: ‎10-10-2007

what's the relationship between MCH OPB_DDR2 and MPMC?

In edk 9.1i , I read some document about MCH OPB_DDR2. But after installed a EDK9.2 , for DDR2 control , only MPMC is available? I just want to use a controller to test my ddr2 ,write some data then read them out and compare them? Which controller should i use ? I am confused about which bus i should use ? and what's the difference if i connect the controller to OPB BUS or PLB bus?
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Xilinx Employee
Xilinx Employee
5,978 Views
Registered: ‎08-08-2007

The memory controller is only a means of communication between the bus and the memory.  In EDK 9.2, there is a new bus protocol being used, the PLBv46.  The MPMC controller that is used in 9.2 communicates on the PLBv46 bus.  In 9.1, there was a different 'multi-port' memory controller to communicate on the OPB bus.

Steve

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