what's the relationship between MCH OPB_DDR2 and MPMC?
In edk 9.1i , I read some document about MCH OPB_DDR2. But after installed a EDK9.2 , for DDR2 control , only MPMC is available? I just want to use a controller to test my ddr2 ,write some data then read them out and compare them? Which controller should i use ? I am confused about which bus i should use ? and what's the difference if i connect the controller to OPB BUS or PLB bus?
The memory controller is only a means of communication between the bus and the memory. In EDK 9.2, there is a new bus protocol being used, the PLBv46. The MPMC controller that is used in 9.2 communicates on the PLBv46 bus. In 9.1, there was a different 'multi-port' memory controller to communicate on the OPB bus.