UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
4,002 Views
Registered: ‎12-29-2008

will DCM output affects the overall frequency of the design??????

Hi,

I have a design which is to be tested at 200mhz, but my board (ml403) will give reference clock of 100mhz , so i have used dcm to multiply the frequency. First i have used both frequencies (input to DCM and output from DCM as 100mhz) same , then the frequency of complete design is 269 mhz, when i increase this output frequency to 150mhz then then frequency of complete design came down to 132 mhz. Please let me know why it happens, am i doing any mistake??

 

**I am using ISE 10.1.3. on linux.

 

Thanks in advance..

regards,

Krishna Kishore 

0 Kudos
3 Replies
Instructor
Instructor
3,990 Views
Registered: ‎08-14-2007

Re: will DCM output affects the overall frequency of the design??????

Which report are you using to find the "frequency of complete design?"  The only meaningful number is from the post

place&route timing report.

 

A couple other things to note:

 

1) without timing constraints you can have a wide range of frequency from run to run.  This is due to the random

nature of initial placement, and the fact that without timing constraints the place&route program will not spend

much effort to optimise placement or routing.

 

2) The "maximum frequency" specified may refer to the input clock frequency as the tools understand

that the internal logic runs at some multiple of this clock as defined by the DCM parameters.   If this is

the case, your two frequency numbers may be roughly equivalent.  i.e. in the first case  you cave 269 MHz

multiplied by 1 (same frequency in and out of DCM).  In the second case you have 132 MHz multiplied

byt 1.5 or 198 MHz on the internal clock.

 

Regards,

Gabor

-- Gabor
0 Kudos
Explorer
Explorer
3,982 Views
Registered: ‎12-29-2008

Re: will DCM output affects the overall frequency of the design??????

Thank you Gabor,

 

After synthesizing , what ever number it shows on console, or what ever number it shows on synthesis report, regarding that i am talking.

 

After post place and route will it give the frequency at which the design work, i have seen the report , i didnt find any such details please do guide me in this regard, if i am going in wrong direction.

 

The frequency that your talking (269 mhz )  is not output from the DCM. DCM output is only 100mhz in that case. i.e . suppose if you take system.v is a top file  in that my design ( dut.v) and DCM are instantiated . For system.v (its like wrapper around dut.v and DCM as it is having some external interface), as top file i have synthesized then i got 269mhz as frequency in one case, when i increase DCM out put to 150mhz by changing multiplier and divisor then frequency came down to 132mhz. 

 

If my interpretation of the system and the logic is wrong , please do correct me . I respect your valuable feedback.

regards,

Krishna Kishore 

0 Kudos
Instructor
Instructor
3,979 Views
Registered: ‎08-14-2007

Re: will DCM output affects the overall frequency of the design??????

 

"After synthesizing , what ever number it shows on console, or what ever number it shows on synthesis report, regarding that i am talking."

 

The number from synthesis is only an estimate.  You really want to look at the post place&route timing report or at least the timing

summary at the end of the place&route report.

 

"The frequency that your talking (269 mhz )  is not output from the DCM. DCM output is only 100mhz in that case. i.e . suppose if you take system.v is a top file  in that my design ( dut.v) and DCM are instantiated . For system.v (its like wrapper around dut.v and DCM as it is having some external interface), as top file i have synthesized then i got 269mhz as frequency in one case, when i increase DCM out put to 150mhz by changing multiplier and divisor then frequency came down to 132mhz. "

 

269 MHz represents the best estimate of the maximum frequency at which you could run the design.   Without looking at the details of

the second report, I can't tell whether 132 MHz is the maximum internal  clock frequency or the maximum external clock frequency.  In

one instance this would mean that the internal global clock net and your logic runs at 132 MHz.  In the other instance it would mean

that your logic runs 1.5 times this rate or 198 MHz maximum.  Again, if this came from the synthesis report it is only an estimate.

 

Regards,

Gabor

-- Gabor
0 Kudos