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Observer fk5747
Observer
6,266 Views
Registered: ‎07-03-2011

xst 2033 error, port I is connected to GND

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hi everybody

I am trying to write my custom ip which is supposed to have a communication with a Analoge to digital converter chip.I am using EDK 12.3. in my user_logic.vhd I have this part of code :

  port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
   .
   .
   .
   ADC_CLK_P        :    in  std_logic ;
   ADC_CLK_N        :    in  std_logic ;
   .
   .
     );

and then :

begin
   C1: for I in 0 to 15 generate--FIXME
        IBUFDS_INS :IBUFDS
        generic map (DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25")
       port map (I=>ADC_DP(I) , IB=>ADC_DN(I) , O => x(I));
    end generate;

 

after generating bitstream, the following error happend :

</opt/Xilinx/12.3/ISE_DS/ISE/spartan3/data/spartan3.acd>
ERROR:Xst:2033 - Port I of Input buffer fifo_add_2_0/C1[0].IBUFDS_INS is connected to GND
ERROR:Xst:2033 - Port IB of Input buffer fifo_add_2_0/C1[0].IBUFDS_INS is connected to GND
ERROR:Xst:2033 - Port I of Input buffer fifo_add_2_0/C1[1].IBUFDS_INS is connected to GND
ERROR:Xst:2033 - Port IB of Input buffer fifo_add_2_0/C1[1].IBUFDS_INS is connected to GND

 

as you see the port I and IB are not connected to GND so why this error happened?
I've searched a lot but I do not find any answer.

Please help me.
thank you in advance

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
7,753 Views
Registered: ‎02-01-2008

Re: xst 2033 error, port I is connected to GND

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In your port list you need something like:

ADC_DP : in std_logic_vector(0 to 15);

ADC_DN: in std_logic_vector(0 to 15);

 

Then in the top hdl of the pcore that instantiate user_logic you need to ripple these 32 signals to the top of the pcore hdl. Also add the signals to the pcore's .mpd file.

 

Next, make sure you connect the signals from the pcore to external pins.

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4 Replies
Xilinx Employee
Xilinx Employee
7,754 Views
Registered: ‎02-01-2008

Re: xst 2033 error, port I is connected to GND

Jump to solution

In your port list you need something like:

ADC_DP : in std_logic_vector(0 to 15);

ADC_DN: in std_logic_vector(0 to 15);

 

Then in the top hdl of the pcore that instantiate user_logic you need to ripple these 32 signals to the top of the pcore hdl. Also add the signals to the pcore's .mpd file.

 

Next, make sure you connect the signals from the pcore to external pins.

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Observer fk5747
Observer
6,259 Views
Registered: ‎07-03-2011

Re: xst 2033 error, port I is connected to GND

Jump to solution

thank you for your quick reply.

 

yes you are right, I should instantiate the ports to the top level and make them external in EDK , then generate bitstream.

but I have another problem. in another part of my code these lines :

 

 

  signal  CLK_IBUFG           :  std_logic ;

  begin

 

       IBUFGDS_INS: IBUFGDS    
       generic map (DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25")
       port map (I => ADC_CLK_P , IB => ADC_CLK_N , O => CLK_IBUFG);
       U3: BUFG port map (CLK_IBUFG, ADC_CLK); 

 

and now this error happened:

ERROR:Xst:528 - Multi-source in Unit <user_logic> on signal <CLK_IBUFG>; this signal is connected to multiple drivers.

 

I do not use CLK_IBUFG in any part of my code again and it is a signal, so what's the problem?

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Xilinx Employee
Xilinx Employee
6,248 Views
Registered: ‎02-01-2008

Re: xst 2033 error, port I is connected to GND

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But you do have a short. The default assignment for a bufg is BUFG(O, I).

 

So I strongly suggest you always use:

 

U3: BUFG port map (I => CLK_IBUFG, O => ADC_CLK);

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Observer fk5747
Observer
6,242 Views
Registered: ‎07-03-2011

Re: xst 2033 error, port I is connected to GND

Jump to solution

thanks again, it solves my problem

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