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Explorer
Explorer
6,788 Views
Registered: ‎07-30-2009

zc702 pin out question

so i notice for zc702 DDR, there is no constraint for ddr_dqs_n/p or the ddr_we_n after i generate the PS project.  is it just doesn't use it or its missing?  if so anyone know the pin io standard and location for  dqs and we_n  for zc702  thanks

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2 Replies
Xilinx Employee
Xilinx Employee
6,775 Views
Registered: ‎07-31-2012

Re: zc702 pin out question

Hi,

 

you can check the master XDC for the mig ddr signals and the IO standards assigned. here is the link to hte master XDC for zc702 - link

Thanks,
Anirudh

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Moderator
Moderator
6,763 Views
Registered: ‎07-31-2012

Re: zc702 pin out question

Hi,

 

There is constraint for ddr_dqs_n/p by default when you add zynq IP in your design.  You can verify the relevant constraint file for the processing system IP in Libraries tab -> <block_design_name> -> processing_system_0.xdc. See the attached figure.

 

Refer to http://www.xilinx.com/support/documentation/boards_and_kits/zc702_zvik/ug850-zc702-eval-bd.pdf page 17 for DDR component pin constraints.

 

Regards

Praveen

 

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zynqPS_constraints.jpg
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