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kalyani123
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Registered: ‎11-13-2018

10 g ethernet tcp/ip stack implementation

Hi,

This is related to the Xilinx app notes 1305 and 1306 Designs.I am trying to make these projects work on RFSOC to fully bring up a TCP server working with a 10g Ethernet link so the pl Ethernet 10g and pl Ethernet 1g seem to be good reference points to start with.

My original application requires me to send some pure streaming data after turning it into TCP/IP packets over the 10g Ethernet link. So the plan to implement is, the S2MM interface of DMA Controller,will write into the memory and then packetize it and send through the MM2S interface of DMA which feeds to the 10g ethernet MAC.

In both the app-notes the lock design employs a DMA controller and we are told in the 1306 document that LW/IP library handles the DMA transfers and we are also told that the AXI DMA controller driver must be disabled in Petalinux. the wiki link for both the appnotes is:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841830/PS+and+PL+based+Ethernet+in+Zynq+MPSoC

Screenshot from 2020-05-14 12-53-37.png

 

1306.png

 

 

 

 

 

 

1306_bd.png

 

 

 

 

 

 

 

Can anyone from Xilinx give more clarity as to how the AXI DMA transfers are facilitated.

Finally the design is supposed to sit on a virtex board. So i need to know if the software provided in the 1306 reference design file folder can be ported to a microblaze processor as well.

Thanks

 

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