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Registered: ‎09-06-2019

AXI Interrupt controller reference for custom driver in device tree

Hi we have a block diagram with the AXI INTC in the PL connected to a pin used fo externally referencing a active low edge triggered interrupt. We are trying to implement our custom driver to handle this event and are unsure how to reference the interrupt correctly.

Here is the generated device tree for the axi interrupt controller in the pl:


		axi_intc_0: interrupt-controller@a0001000 {
			#interrupt-cells = <2>;
			clock-names = "s_axi_aclk";
			clocks = <&zynqmp_clk 71>;
			compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a";
			interrupt-controller ;
			reg = <0x0 0xa0001000 0x0 0x1000>;
			xlnx,kind-of-intr = <0x3>;
			xlnx,num-intr-inputs = <0x2>;

The external interrupt source is connected to interrupt position 0 and the axi intc is configured as an active low edge triggered source in the GUI, which is reflected in the device tree. What do we need to reference in the node for our custom driver for the second parameter in the interrupts =<0 ???> property? I know only active high levels are valid for shared processor interrupts (i.e. 0x1 and 0x4) for linux using the GIC but I don't belive the axi intc has this restriction as it should be generating the correct type of interrupt, is this understanding correct?


  The #interrupt-cells property is set to 2 and the first cell defines the
  index of the interrupt within the controller, while the second cell is used
  to specify any of the following flags:
    - bits[3:0] trigger type and level flags
        1 = low-to-high edge triggered
        2 = high-to-low edge triggered
        4 = active high level-sensitive
        8 = active low level-sensitive

My intuition tells me that the interrupt properties for our node should simply be the following (assuming the active low edge triggered interrupt source is routed to int 0) Resulting in the following device tree node:


&spi1     {
                status = "okay";
                num-cs = <1>;
                label = "SPI_1";
                is-decoded-cs = <0>;
                custom_ic_driver: spi_device@0 {
                                reg = <0>;
                                interrupt-parent = <&intc>; /* Interrupt parent = axi intc */
                                interrupts = <0 2>; /* interrupt 0, edge triggered active low */
... }

Another source of confusion is if the second parameters of interrupts is even required. The bindings documentation for the xlnx,xps-intc-1.00.a compatible driver states the following:

- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
		     interrupt source. The value shall be a minimum of 1.
		     The Xilinx device trees typically use 2 but the 2nd value
		     is not used.

I'm assuming the second parameter is not required due to the fact that the axi intc itself has already been configured to trigger on the correct interrupt type and therefore does not have to be set in the device tree. Can someone confirm this?

Thanks in advance!



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5 Replies
Registered: ‎09-12-2007

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Registered: ‎09-06-2019


The referenced page utilizes the UIO and AXI GPIO block with the IRQ directly connect to the PL-PS interrupt ports, the documention doesn't explain the usage of the AXI INTC ip but rather using the gpio as an interrupt. This results in the device tree as a gic interrupt parent. What I'm interested in is implementing our custom node using a axi_intc interrupt parent. Is there an equivalent reference using the AXI INTC in particular? 

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Registered: ‎10-21-2015

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Registered: ‎09-06-2019


Thanks for the reference. Could you clarify how you calculated the GIC IRQ ID in your device tree node? (I'm testing the same block diagram architecture from the linked forum post)

amba_pl {

        interrupt-controller@80000000 {
            #interrupt-cells = <0x2>;
            clock-names = "s_axi_aclk";
            clocks = <0x3 0x47>;
            compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a";
            reg = <0x0 0x80000000 0x0 0x10000>;
            xlnx,kind-of-intr = <0x0>;
            xlnx,num-intr-inputs = <0x1>;
            interrupt-parent = <0x4>;
            interrupts = <0x0 0x59 0x4>;
            phandle = <0x20>;

I'm having difficulty figuring out the correct IRQ ID # to set in the device tree.The Ultrascale+ documentation has the following table:


In which my design results in my interrupt being connected to IRQ121 but I've seen documentation that for the device tree entry the GIC mapping is in fact IRQ ID - 32. So for my case it seems like my IRQ ID would need to be 121-32=89 like so:

interrupts=<0 89 4>;

Looking at the device tree source code it seems like this should be the correct method. Starting on line 3830 of the device-tree-xlnx repo (2019.1) it seems like the IRQ ID-32 is the correct way to map PL-PS interrupts into the device tree nodes:

    set intr_list_irq0 [list 89 90 91 92 93 94 95 96]
    set intr_list_irq1 [list 104 105 106 107 108 109 110 111]

Can you confirm that this in fact is the correct method? 


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Registered: ‎10-21-2015

Hi @badFITimage 

Your calculation is correct

Refer to