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Registered: ‎09-17-2013

Dual hdmi vid_PHY_controller problem - Xilinx LInux

 

Dual hdmi vid_PHY_controller divce_tree problem:

[ 10.260017] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: failed to get phy lane hdmi-phy0 index 0, error -19
[ 10.269095] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: probe failed:: error_phy:
[ 10.276506] xilinx-hdmi-rx a0000000.hdmi_rx_ss: probed
[ 10.282702] xilinx-hdmi-rx a0000000.hdmi_rx_ss: failed to get phy lane hdmi-phy0 index 0, error -19

 

#ifdef CONFIG_HDMI1_RX
#include "vcap-hdmi_2.dtsi"
#endif
#ifdef CONFIG_HDMI_RX
#include "vcap-hdmi_1.dtsi"
#endif
#ifdef CONFIG_HDMI_TX
#include "hdmi-misc.dtsi"
#include "drm-hdmi.dtsi"
#endif
#ifdef CONFIG_HDMI1_TX
#include "hdmi-misc1.dtsi"
#include "drm-hdmi1.dtsi"
#endif
#include "vcu.dtsi"
#include "apm.dtsi"
&amba {
 vid_stream_clk: vid_stream_clk {
  compatible = "fixed-clock";
  #clock-cells = <0>;
  clock-frequency = <300000000>;
 };
 vid_s_axi_clk: vid_s_axi_clk {
  compatible = "fixed-clock";
  #clock-cells = <0>;
  clock-frequency = <99990000>;
 };
 
#if defined(CONFIG_SDI_RX)
 misc_clk_0: misc_clk_0 {
  compatible = "fixed-clock";
  #clock-cells = <0>;
  clock-frequency = <100000000>;
 };
#endif
#if defined(CONFIG_HDMI_RX) || defined(CONFIG_HDMI_TX) || defined(CONFIG_DM1)
 vid_phy_controller: vid_phy_controller@a0060000 {
  compatible = "xlnx,vid-phy-controller-2.2";
  interrupt-parent = <&gic>;
  interrupts = <0 92 4>;
  reg = <0x0 0xa0060000 0x0 0x10000>;
  clocks = <&vid_s_axi_clk>, <&si570_2>;
  clock-names = "axi-lite", "dru-clk";
  xlnx,input-pixels-per-clock = <0x2>;
  xlnx,nidru = <0x1>;
  xlnx,nidru-refclk-sel = <0x5>;
  xlnx,rx-no-of-channels = <0x3>;
  xlnx,rx-pll-selection = <0x0>;
  xlnx,rx-protocol = <0x1>;
  xlnx,rx-refclk-sel = <0x1>;
  xlnx,tx-no-of-channels = <0x3>;
  xlnx,tx-pll-selection = <0x6>;
  xlnx,tx-protocol = <0x1>;
  xlnx,tx-refclk-sel = <0x0>;
  xlnx,hdmi-fast-switch = <0x1>;
  xlnx,transceiver-type = <0x5>;
  xlnx,tx-buffer-bypass = <0x1>;
  xlnx,transceiver-width = <0x2>;
  vphy_lane0: vphy_lane@0 {
   #phy-cells = <4>;
  };
  vphy_lane1: vphy_lane@1 {
   #phy-cells = <4>;
  };
  vphy_lane2: vphy_lane@2 {
   #phy-cells = <4>;
  };
  vphy_lane3: vphy_lane@3 {
   #phy-cells = <4>;
  };
 };
#endif
 
#if defined(CONFIG_HDMI1_RX) || defined(CONFIG_HDMI1_TX)
 vid_phy_controller_0: vid_phy_controller@a0240000 {
  compatible = "xlnx,vid-phy-controller-2.2";
  interrupt-parent = <&gic>;
  interrupts = <0 105 4>;
  reg = <0x0 0xa0240000 0x0 0x10000>;
  clocks = <&vid_s_axi_clk>, <&si570_2>;
  clock-names = "axi-lite", "dru-clk";
  xlnx,input-pixels-per-clock = <0x2>;
  xlnx,nidru = <0x1>;
  xlnx,nidru-refclk-sel = <0x5>;
  xlnx,rx-no-of-channels = <0x3>;
  xlnx,rx-pll-selection = <0x0>;
  xlnx,rx-protocol = <0x1>;
  xlnx,rx-refclk-sel = <0x0>;
  xlnx,tx-no-of-channels = <0x3>;
  xlnx,tx-pll-selection = <0x6>;
  xlnx,tx-protocol = <0x1>;
  xlnx,tx-refclk-sel = <0x4>;
  xlnx,hdmi-fast-switch = <0x1>;
  xlnx,transceiver-type = <0x5>;
  xlnx,tx-buffer-bypass = <0x1>;
  xlnx,transceiver-width = <0x2>;
  vphy_lane4: vphy_lane@0 {
   #phy-cells = <4>;
  };
  vphy_lane5: vphy_lane@1 {
   #phy-cells = <4>;
  };
  vphy_lane6: vphy_lane@2 {
   #phy-cells = <4>;
  };
  vphy_lane7: vphy_lane@3 {
   #phy-cells = <4>;
  };
 };
#endif
};

 

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