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Observer
Observer
6,674 Views
Registered: ‎10-28-2013

Dual phys on MDIO/EMIO

We have 2 custom zynq boards. One board uses phy0 on MDIO and phy1 on EMIO. The second board uses both on a single MDIO.  I grabbed the patch from https://forums.xilinx.com/t5/Embedded-Linux/Dual-Marvell-88e1512-PHY-Ethernet-problem-Xilinx-LInux/m-p/728828/highlight/false#M17179 to get the dual phys working on a single MDIO with linux-xlnx 2016.1. However now we can't attach to phy1 on EMIO on our first board (we could before the patch). We really want to use a single kernel between the two boards to keep our setup as simple as can be.

 

Before the patch our device tree looked like this for a phy on MDIO and one on EMIO:

 

&gem0 {
	local-mac-address = [00 4a 35 00 0e 05];
	phy-mode = "rgmii-id";
	status = "okay";
	phy-handle = <&phy0>;
	xlnx,enet-reset = <0xffffffff>;
	xlnx,eth-mode = <0x1>;
	xlnx,ptp-enet-clock = <0x69f6bcb>;
	phy0: phy@0 {
		compatible = "marvell,88e1510";
		device_type = "ethernet-phy";
		reg = <0>;
	};
};
&gem1 {
	local-mac-address = [00 0a 35 00 0f 0a];
	phy-mode = "gmii";
	status = "okay";
	phy-handle = <&phy1>;
	xlnx,enet-reset = <0xffffffff>;
	xlnx,eth-mode = <0x1>;
	xlnx,ptp-enet-clock = <0x69f6bcb>;
	phy1: phy@1 {
		compatible = "ethernet-phy-id0174.0C01";
		device_type = "ethernet-phy";
		xlnx,phy-type = <5>;
		reg = <1>;
	};
};

 Thoughts on how to make it work for both boards?

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7 Replies
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Xilinx Employee
Xilinx Employee
6,631 Views
Registered: ‎08-01-2008

Re: Dual phys on MDIO/EMIO

check these links
https://www.xilinx.com/support/answers/59554.html
https://forums.xilinx.com/t5/Embedded-Linux/Dual-EMIO-ethernet-with-single-EMIO/td-p/685570
https://forums.xilinx.com/t5/Embedded-Linux/Dual-Marvell-88e1512-PHY-Ethernet-problem-Xilinx-LInux/td-p/682660/page/3
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
6,603 Views
Registered: ‎07-01-2010

Re: Dual phys on MDIO/EMIO

@lancec

 

What is the kernel version used?

 

I see MDIO node missing in the device-tree.Refer to the example MDIO configuration in the link.

 

Regards,

Achutha

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Observer
Observer
6,551 Views
Registered: ‎10-28-2013

Re: Dual phys on MDIO/EMIO

I'm running on the Xilinx 2016.1 tag. I know the mdio node is missing in what I posted. It was what was there when I took over the project and worked until I patched my kernel to work with 2 phys on a single mdio. However even when I added it in it still did not work. If you look at the link I posted ( @balkris posted it too), it moves the mdio node location in the devicetree. I have tried several varations and placements of the mdio node and have to been able to get the emio phy to work.

 

 

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Observer
Observer
4,778 Views
Registered: ‎10-28-2013

Re: Dual phys on MDIO/EMIO

I'm back at trying to get this working. I've updated to the Xilinx 2017.2 tag and have added in the official Xilinx patch:

https://www.xilinx.com/support/answers/69132.html.

 

I have both phys working on the second board with a single MDIO. The first board I have the phy on the MIO working, but I cannot get the phy on the EMIO to work. How do I get the EMIO phy to work?

 

 

Here is the relevant part of my devicetree for that board.

/dts-v1/;
/include/ "zynq-7000.dtsi"
/include/ "vehicle_pl.dtsi"
/ {
	cpus {
		cpu@0 {
			operating-points = <666666 1000000 333333 1000000>;
		};
	};
	chosen {
		bootargs = "console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext2,ext3,ext4,vfat rootwait devtmpfs.mount=1";
	};
	aliases {
		ethernet0 = &gem0;
		ethernet1 = &gem1;
		serial0 = &uart0;
		spi0 = &qspi;
	};
	memory {
		device_type = "memory";
		reg = <0x0 0x40000000>;
	};
	rspi {
		compatible = "cse_charlie-01";
		flavor = "top";
		interrupt-parent = <&intc>;
		interrupts = <0 29 4>, <0 30 1>, <0 31 1>, <0 32 1>;
	};
	mdio {
		compatible = "cdns,macb-mdio";
		reg = <0xe000b000 0x1000>;
		clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
		clock-names = "pclk", "hclk", "tx_clk";
		#address-cells = <1>;
		#size-cells = <0>;
		phy0: phy@0 {
		     reg = <0>;
		};
	};
};
&gem0 {
	local-mac-address = [00 4a 35 00 0e 05];
	phy-mode = "rgmii-id";
	status = "okay";
	phy-handle = <&phy0>;
	xlnx,enet-reset = <0xffffffff>;
	xlnx,eth-mode = <0x1>;
	xlnx,ptp-enet-clock = <0x69f6bcb>;
};
&gem1 {
	local-mac-address = [00 0a 35 00 0f 0a];
	phy-mode = "gmii";
	status = "okay";
	phy-handle = <&phy1>;
	xlnx,enet-reset = <0xffffffff>;
	xlnx,eth-mode = <0x1>;
	xlnx,ptp-enet-clock = <0x69f6bcb>;
	phy1: phy@1 {
		compatible = "ethernet-phy-id0174.0C01";
		device_type = "ethernet-phy";
		xlnx,phy-type = <5>;
		reg = <1>;
	};
};

 

 

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Participant
Participant
4,247 Views
Registered: ‎03-09-2016

Re: Dual phys on MDIO/EMIO

Hi,

 

I have also same issue; our custom board has two ethernet switch; one is connected to GEM0 and its mdio is thorugh MIO pins; other one is connected to GEM1 and its mdio is through EMIO pins. Petalinux version is 2017.2. Our situation is like that;

 

* Using this patch (https://www.xilinx.com/support/answers/69132.html) and only GEMO is enabled from the vivado, it works.

* Using this patch (https://www.xilinx.com/support/answers/69132.html) and only GEM1 is enabled from the vivado, it also works.

* Using this patch (https://www.xilinx.com/support/answers/69132.html) and GEM0 and GEM1 is enabled from the vivado as in your case, GEM0 works but GEM1 does not work. GEM1 mdio could not found phy.

 

If you have solved your problem, could you share the solution?

thanks,

 

 

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Highlighted
Observer
Observer
4,233 Views
Registered: ‎10-28-2013

Re: Dual phys on MDIO/EMIO

We have not found a solution. We're still using 2016.1 and the patch I referenced in my original post. I would love to find a solution.

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Newbie
Newbie
2,923 Views
Registered: ‎04-10-2018

Re: Dual phys on MDIO/EMIO

In our system, we have two TI PHYs hooked up to the MDIO bus of eth0.  We experienced the same problem described here and elsewhere.

 

We are using a stock linux 4.14.32 kernel with the files in drivers/net/ethernet/cadence/ being replaced with the ones from the xilinx petalinux git pull.

 

The main problem appears to be that the node pointed to by "phy-handle" in the device tree is ignored and the macb driver ends up scanning its bus for the first available PHY.

 

Our fix was to add a single line to macb_main.c.  This is the patch:

 

diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index 2624fc2..8ae900f 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -3774,10 +3774,11 @@ static int macb_probe(struct platform_device *pdev)
                int gpio = of_get_named_gpio(phy_node, "reset-gpios", 0);
                if (gpio_is_valid(gpio)) {
                        bp->reset_gpio = gpio_to_desc(gpio);
                        gpiod_direction_output(bp->reset_gpio, 1);
                }
+               bp->phy_node = phy_node;                // this fixes the problem of 2 PHYs on 1 MDIO bus
        }
 
        err = of_get_phy_mode(np);
        if (err < 0) {
                pdata = dev_get_platdata(&pdev->dev);

 

This is the relevant part of the device tree:

 

 

  eth0@e000b000 {
    compatible = "cdns,gem";
    reg = <0xe000b000 0x1000>;
    status = "okay";
    interrupts = <0x0 0x16 0x4>;
    clocks = <0x1 0x1e 0x1 0x1e 0x1 0xd>;
    clock-names = "pclk", "hclk", "tx_clk";
    phy-mode = "rgmii";
    xlnx,ptp-enet-clock = <0x69f6bcb>;
    phy-handle = <&mdio0>;
    #address-cells = <1>;
    #size-cells = <0>;

    mdio0: mdio_at_addr_0@0 {
      reg = <0>;
      ti,rx-internal-delay = <0x7>;   //DP83867_RGMIIDCTL_2_00_NS
      ti,tx-internal-delay = <0x3>;   //DP83867_RGMIIDCTL_1_NS
      ti,fifo-depth = <0x03>;         //DP83867_PHYCR_FIFO_DEPTH_8_B_NIB
    };
    mdio1: mdio_at_addr_1@1 {
      reg = <1>;
      ti,rx-internal-delay = <0x7>;   //DP83867_RGMIIDCTL_2_00_NS
      ti,tx-internal-delay = <0x3>;   //DP83867_RGMIIDCTL_1_NS
      ti,fifo-depth = <0x03>;         //DP83867_PHYCR_FIFO_DEPTH_8_B_NIB
}; }; eth1@e000c000 { compatible = "cdns,gem"; reg = <0xe000c000 0x1000>; status = "okay"; interrupts = <0x0 0x2d 0x4>; clocks = <0x1 0x1f 0x1 0x1f 0x1 0xe>; clock-names = "pclk", "hclk", "tx_clk"; phy-mode = "rgmii"; phy-handle = <&mdio1>; };

 

There is no guarantee that the described kernel modification will not break something else, but it enabled us to get our configuration working.

 

 

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