cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
265 Views
Registered: ‎05-04-2018

How ZYNQ Ultrascale's PS part load its voltage

Hello.

I found that when I configure the ZU7CG PS voltage in I/O Configuration, for example, I set Bank0 to LVCMOS18, Bank1 to LVCMOS33.

However, when I generate the hdf file, I found that when I config the bank voltage to 3.3V or 1.8V, I will get the same ps7_init.tcl and ps7_init.c.

So I wonder how the PS part config its bank voltage through the hdf file.

                        

                                        Thank you

 

0 Kudos
5 Replies
Highlighted
Advisor
Advisor
248 Views
Registered: ‎02-12-2013

I don't think that those PS startup scripts can do anything about I/O supply voltages. Those settings affect the FPGA logic design and your board design but the software tools should not need to consider them.

Correct me if I am wrong about this.

----------------------------------------
DSP in hardware and software
-----------------------------------------
0 Kudos
Highlighted
243 Views
Registered: ‎05-04-2018

Thanks for your reply

However, if I only printf a "hellow world", I don't need the .bit file. I only generate the .elf file then I can boot the PS. So I think there is no relation between PS bank's voltage and the .bit file.

 

Looking forward to your reply

0 Kudos
Highlighted
230 Views
Registered: ‎06-21-2017

I haven't searched all of the files in the hdf, but you can find the PS side IO settings in the hwh file.  I don't know how important these settings are.  If the pins are outputs, they will probably drive to within a couple hundred mV of the VCCO rail.  As inputs, these will be diode clamped to VCCO and GND.  The switch point may be tied to VCCO, not the setting.  I don't know the internals of the circuit.

0 Kudos
Highlighted
197 Views
Registered: ‎05-04-2018

Thanks for your reply again

   May I think about it in this way: the PS's bank's voltage, in fact, is set up to configure the peripheral components on the PL. And the devices which link to the PS's banks directly have no relationship with this settings?

    Due to your advice, I've read the .hwh file and the tcl file created after the .hwh, and I found that it guide the .bd file and created the wrapper.v finally. However, .v file only affect the PL's componenets. So is my comprehension right?

    Looking forwart to you reply. Thank you.

0 Kudos
Highlighted
191 Views
Registered: ‎06-21-2017

This information is also in the <DesignName>_bd.tcl file in the sources_1\bd\<DesignName\hw_handoff folder.

 

  # Create instance: zynq_ultra_ps_e_0, and set properties
  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
  set_property -dict [ list \
   CONFIG.CAN0_BOARD_INTERFACE {custom} \
   CONFIG.CAN1_BOARD_INTERFACE {custom} \
   CONFIG.CSU_BOARD_INTERFACE {custom} \
   CONFIG.DP_BOARD_INTERFACE {custom} \
   CONFIG.GEM0_BOARD_INTERFACE {custom} \
   CONFIG.GEM1_BOARD_INTERFACE {custom} \
   CONFIG.GEM2_BOARD_INTERFACE {custom} \
   CONFIG.GEM3_BOARD_INTERFACE {custom} \
   CONFIG.GPIO_BOARD_INTERFACE {custom} \
   CONFIG.IIC0_BOARD_INTERFACE {custom} \
   CONFIG.IIC1_BOARD_INTERFACE {custom} \
   CONFIG.NAND_BOARD_INTERFACE {custom} \
   CONFIG.PCIE_BOARD_INTERFACE {custom} \
   CONFIG.PJTAG_BOARD_INTERFACE {custom} \
   CONFIG.PMU_BOARD_INTERFACE {custom} \
   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS25} \
   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
0 Kudos