cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
bfung_2
Adventurer
Adventurer
420 Views
Registered: ‎07-02-2020

Linux Boot smp_twd: clock not found -2

I've created a device tree using Xilinx SDK 14.7 based off of a design created in PlanAhead 14.7.

Next, I created a boot.bin linux image for SD Card boot.

The Kernel boots until the following error messages appear:

 

Starting kernel ...

Booting Linux on physical CPU 0x0
Linux version 3.9.0-xilinx (tom@localhost.localdomain) (gcc version 4.7.3 20130328 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2013.04-20130415 - Linaro GCC 2013.04) ) #1 SMP PREEMPT Tue May 20 21:27:45 PDT 2014
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Xilinx Zynq Platform, model: Xilinx Zynq
bootconsole [earlycon0] enabled
cma: CMA: reserved 16 MiB at 2e800000
Memory policy: ECC disabled, Data cache writealloc
PERCPU: Embedded 7 pages/cpu @c0de9000 s8128 r8192 d12352 u32768
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 260624
Kernel command line: console=ttyPS0,115200 root=/dev/mmcblk0p2 rootwait rw earlyprintk rootfstype=ext4 devtmpfs.mount=0 ip=:::::eth0:dhcp
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
__ex_table already sorted, skipping sort
Memory: 1024MB = 1024MB total
Memory: 1017020k/1017020k available, 31556k reserved, 270336K highmem
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    vmalloc : 0xf0000000 - 0xff000000   ( 240 MB)
    lowmem  : 0xc0000000 - 0xef800000   ( 760 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .text : 0xc0008000 - 0xc054b1e4   (5389 kB)
      .init : 0xc054c000 - 0xc0576fc0   ( 172 kB)
      .data : 0xc0578000 - 0xc05b4a40   ( 243 kB)
       .bss : 0xc05b4a40 - 0xc05df4b0   ( 171 kB)
Preemptible hierarchical RCU implementation.
	Dump stacks of tasks blocking RCU-preempt GP.
	RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
NR_IRQS:16 nr_irqs:16 16
xslcr mapped to f0002000
Zynq clock init
smp_twd: clock not found -2
Division by zero in kernel.
[<c001459c>] (unwind_backtrace+0x0/0x11c) from [<c01ac0b0>] (Ldiv0_64+0x8/0x18)
[<c01ac0b0>] (Ldiv0_64+0x8/0x18) from [<c0051a0c>] (__clocksource_updatefreq_scale+0x30/0x100)
[<c0051a0c>] (__clocksource_updatefreq_scale+0x30/0x100) from [<c0051ae8>] (__clocksource_register_scale+0xc/0x44)
[<c0051ae8>] (__clocksource_register_scale+0xc/0x44) from [<c0564b50>] (ttc_timer_init+0x124/0x370)
[<c0564b50>] (ttc_timer_init+0x124/0x370) from [<c0564970>] (clocksource_of_init+0x20/0x44)
[<c0564970>] (clocksource_of_init+0x20/0x44) from [<c054fd50>] (time_init+0x14/0x20)
[<c054fd50>] (time_init+0x14/0x20) from [<c054c6bc>] (start_kernel+0x1b0/0x2ec)
[<c054c6bc>] (start_kernel+0x1b0/0x2ec) from [<00008074>] (0x8074)
Division by zero in kernel.
[<c001459c>] (unwind_backtrace+0x0/0x11c) from [<c01ac0b0>] (Ldiv0_64+0x8/0x18)
[<c01ac0b0>] (Ldiv0_64+0x8/0x18) from [<c00519a8>] (clocks_calc_mult_shift+0x70/0xa4)
[<c00519a8>] (clocks_calc_mult_shift+0x70/0xa4) from [<c0051a88>] (__clocksource_updatefreq_scale+0xac/0x100)
[<c0051a88>] (__clocksource_updatefreq_scale+0xac/0x100) from [<c0051ae8>] (__clocksource_register_scale+0xc/0x44)
[<c0051ae8>] (__clocksource_register_scale+0xc/0x44) from [<c0564b50>] (ttc_timer_init+0x124/0x370)
[<c0564b50>] (ttc_timer_init+0x124/0x370) from [<c0564970>] (clocksource_of_init+0x20/0x44)
[<c0564970>] (clocksource_of_init+0x20/0x44) from [<c054fd50>] (time_init+0x14/0x20)
[<c054fd50>] (time_init+0x14/0x20) from [<c054c6bc>] (start_kernel+0x1b0/0x2ec)
[<c054c6bc>] (start_kernel+0x1b0/0x2ec) from [<00008074>] (0x8074)
Division by zero in kernel.
[<c001459c>] (unwind_backtrace+0x0/0x11c) from [<c01ac0b0>] (Ldiv0_64+0x8/0x18)
[<c01ac0b0>] (Ldiv0_64+0x8/0x18) from [<c00519a8>] (clocks_calc_mult_shift+0x70/0xa4)
[<c00519a8>] (clocks_calc_mult_shift+0x70/0xa4) from [<c054f0ac>] (setup_sched_clock+0x88/0x20c)
[<c054f0ac>] (setup_sched_clock+0x88/0x20c) from [<c0564ca8>] (ttc_timer_init+0x27c/0x370)
[<c0564ca8>] (ttc_timer_init+0x27c/0x370) from [<c0564970>] (clocksource_of_init+0x20/0x44)
[<c0564970>] (clocksource_of_init+0x20/0x44) from [<c054fd50>] (time_init+0x14/0x20)
[<c054fd50>] (time_init+0x14/0x20) from [<c054c6bc>] (start_kernel+0x1b0/0x2ec)
[<c054c6bc>] (start_kernel+0x1b0/0x2ec) from [<00008074>] (0x8074)
sched_clock: 16 bits at 0 Hz, resolution 0ns, wraps every 0ms
Division by zero in kernel.
[<c001459c>] (unwind_backtrace+0x0/0x11c) from [<c01ac0b0>] (Ldiv0_64+0x8/0x18)
[<c01ac0b0>] (Ldiv0_64+0x8/0x18) from [<c0054530>] (clockevents_config+0x28/0x70)
[<c0054530>] (clockevents_config+0x28/0x70) from [<c005458c>] (clockevents_config_and_register+0x14/0x20)
[<c005458c>] (clockevents_config_and_register+0x14/0x20) from [<c0564ce0>] (ttc_timer_init+0x2b4/0x370)
[<c0564ce0>] (ttc_timer_init+0x2b4/0x370) from [<c0564970>] (clocksource_of_init+0x20/0x44)
[<c0564970>] (clocksource_of_init+0x20/0x44) from [<c054fd50>] (time_init+0x14/0x20)
[<c054fd50>] (time_init+0x14/0x20) from [<c054c6bc>] (start_kernel+0x1b0/0x2ec)
[<c054c6bc>] (start_kernel+0x1b0/0x2ec) from [<00008074>] (0x8074)
------------[ cut here ]------------
WARNING: at kernel/time/clockevents.c:46 clockevent_delta2ns+0x3c/0x84()
Modules linked in:
[<c001459c>] (unwind_backtrace+0x0/0x11c) from [<c0021128>] (warn_slowpath_common+0x4c/0x6c)
[<c0021128>] (warn_slowpath_common+0x4c/0x6c) from [<c0021160>] (warn_slowpath_null+0x18/0x1c)
[<c0021160>] (warn_slowpath_null+0x18/0x1c) from [<c0054130>] (clockevent_delta2ns+0x3c/0x84)
[<c0054130>] (clockevent_delta2ns+0x3c/0x84) from [<c005455c>] (clockevents_config+0x54/0x70)
[<c005455c>] (clockevents_config+0x54/0x70) from [<c005458c>] (clockevents_config_and_register+0x14/0x20)
[<c005458c>] (clockevents_config_and_register+0x14/0x20) from [<c0564ce0>] (ttc_timer_init+0x2b4/0x370)
[<c0564ce0>] (ttc_timer_init+0x2b4/0x370) from [<c0564970>] (clocksource_of_init+0x20/0x44)
[<c0564970>] (clocksource_of_init+0x20/0x44) from [<c054fd50>] (time_init+0x14/0x20)
[<c054fd50>] (time_init+0x14/0x20) from [<c054c6bc>] (start_kernel+0x1b0/0x2ec)
[<c054c6bc>] (start_kernel+0x1b0/0x2ec) from [<00008074>] (0x8074)
---[ end trace 1b75b31a2719ed1c ]---
ps7-ttc #0 at f0004000, irq=43
Console: colour dummy device 80x30
Calibrating delay loop... 

 

This seems to indicate there may be something wrong with finding clock information in the device tree generated, but I'm not sure what exactly.

 

/*
 * Device Tree Generator version: 1.1
 *
 * (C) Copyright 2007-2013 Xilinx, Inc.
 * (C) Copyright 2007-2013 Michal Simek
 * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * CAUTION: This file is automatically generated by libgen.
 * Version: Xilinx EDK 14.7 EDK_P.20131013
 * Today is: Thursday, the 04 of February, 2021; 12:34:09
 *
 * XPS project directory: device-tree_bsp_5
 */

/dts-v1/;
/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "xlnx,zynq-7000";
	model = "Xilinx Zynq";
	aliases {
		ethernet0 = &ps7_ethernet_0;
		serial1 = &ps7_uart_1;
		spi0 = &ps7_qspi_0;
	} ;
	chosen {
		bootargs = "";
	} ;
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		ps7_cortexa9_0: cpu@0 {
			bus-handle = <&ps7_axi_interconnect_0>;
			compatible = "arm,cortex-a9";
			d-cache-line-size = <0x20>;
			d-cache-size = <0x8000>;
			device_type = "cpu";
			i-cache-line-size = <0x20>;
			i-cache-size = <0x8000>;
			interrupt-handle = <&ps7_scugic_0>;
			reg = <0x0>;
		} ;
		ps7_cortexa9_1: cpu@1 {
			bus-handle = <&ps7_axi_interconnect_0>;
			compatible = "arm,cortex-a9";
			d-cache-line-size = <0x20>;
			d-cache-size = <0x8000>;
			device_type = "cpu";
			i-cache-line-size = <0x20>;
			i-cache-size = <0x8000>;
			interrupt-handle = <&ps7_scugic_0>;
			reg = <0x1>;
		} ;
	} ;
	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupt-parent = <&ps7_scugic_0>;
		interrupts = <0 5 4>, <0 6 4>;
		reg = <0xf8891000 0x1000>, <0xf8893000 0x1000>;
		reg-names = "cpu0", "cpu1";
	} ;
	ps7_ddr_0: memory@0 {
		device_type = "memory";
		reg = <0x0 0x40000000>;
	} ;
	ps7_axi_interconnect_0: amba@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "xlnx,ps7-axi-interconnect-1.00.a", "simple-bus";
		ranges ;
		ps7_afi_0: ps7-afi@f8008000 {
			compatible = "xlnx,ps7-afi-1.00.a";
			reg = <0xf8008000 0x1000>;
		} ;
		ps7_afi_1: ps7-afi@f8009000 {
			compatible = "xlnx,ps7-afi-1.00.a";
			reg = <0xf8009000 0x1000>;
		} ;
		ps7_afi_2: ps7-afi@f800a000 {
			compatible = "xlnx,ps7-afi-1.00.a";
			reg = <0xf800a000 0x1000>;
		} ;
		ps7_afi_3: ps7-afi@f800b000 {
			compatible = "xlnx,ps7-afi-1.00.a";
			reg = <0xf800b000 0x1000>;
		} ;
		ps7_coresight_comp_0: ps7-coresight-comp@f8800000 {
			compatible = "xlnx,ps7-coresight-comp-1.00.a";
			reg = <0xf8800000 0x100000>;
		} ;
		ps7_ddrc_0: ps7-ddrc@f8006000 {
			compatible = "xlnx,ps7-ddrc-1.00.a", "xlnx,ps7-ddrc";
			reg = <0xf8006000 0x1000>;
			xlnx,has-ecc = <0x0>;
		} ;
		ps7_dev_cfg_0: ps7-dev-cfg@f8007000 {
			clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
			clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
			compatible = "xlnx,ps7-dev-cfg-1.00.a";
			interrupt-parent = <&ps7_scugic_0>;
			interrupts = <0 8 4>;
			reg = <0xf8007000 0x100>;
		} ;
		ps7_dma_s: ps7-dma@f8003000 {
			#dma-cells = <1>;
			#dma-channels = <8>;
			#dma-requests = <4>;
			arm,primecell-periphid = <0x41330>;
			clock-names = "apb_pclk";
			clocks = <&clkc 27>;
			compatible = "xlnx,ps7-dma-1.00.a", "arm,primecell", "arm,pl330";
			interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
				"dma4", "dma5", "dma6", "dma7";
			interrupt-parent = <&ps7_scugic_0>;
			interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>;
			reg = <0xf8003000 0x1000>;
		} ;
		ps7_ethernet_0: ps7-ethernet@e000b000 {
			#address-cells = <1>;
			#size-cells = <0>;
			clock-names = "ref_clk", "aper_clk";
			clocks = <&clkc 13>, <&clkc 30>;
			compatible = "xlnx,ps7-ethernet-1.00.a";
			interrupt-parent = <&ps7_scugic_0>;
			interrupts = <0 22 4>;
			local-mac-address = [00 0a 35 00 00 00];
			phy-handle = <&phy0>;
			phy-mode = "rgmii-id";
			reg = <0xe000b000 0x1000>;
			xlnx,enet-reset = <0xffffffff>;
			xlnx,eth-mode = <0x1>;
			xlnx,has-mdio = <0x1>;
			xlnx,ptp-enet-clock = <111111115>;
			mdio {
				#address-cells = <1>;
				#size-cells = <0>;
				phy0: phy@7 {
					compatible = "marvell,88e1116r";
					device_type = "ethernet-phy";
					reg = <7>;
				} ;
			} ;
		} ;
		ps7_globaltimer_0: ps7-globaltimer@f8f00200 {
			compatible = "xlnx,ps7-globaltimer-1.00.a";
			reg = <0xf8f00200 0x100>;
		} ;
		ps7_gpio_0: ps7-gpio@e000a000 {
			#gpio-cells = <2>;
			clocks = <&clkc 42>;
			compatible = "xlnx,ps7-gpio-1.00.a";
			emio-gpio-width = <64>;
			gpio-controller ;
			gpio-mask-high = <0xc0000>;
			gpio-mask-low = <0xfe81>;
			interrupt-parent = <&ps7_scugic_0>;
			interrupts = <0 20 4>;
			reg = <0xe000a000 0x1000>;
		} ;
		ps7_gpv_0: ps7-gpv@f8900000 {
			compatible = "xlnx,ps7-gpv-1.00.a";
			reg = <0xf8900000 0x100000>;
		} ;
		ps7_intc_dist_0: ps7-intc-dist@f8f01000 {
			compatible = "xlnx,ps7-intc-dist-1.00.a";
			reg = <0xf8f01000 0x1000>;
		} ;
		ps7_iop_bus_config_0: ps7-iop-bus-config@e0200000 {
			compatible = "xlnx,ps7-iop-bus-config-1.00.a";
			reg = <0xe0200000 0x1000>;
		} ;
		ps7_l2cachec_0: ps7-l2cachec@f8f02000 {
			compatible = "xlnx,ps7-l2cachec-1.00.a";
			reg = <0xf8f02000 0x1000>;
		} ;
		ps7_ocmc_0: ps7-ocmc@f800c000 {
			compatible = "xlnx,ps7-ocmc-1.00.a";
			reg = <0xf800c000 0x1000>;
		} ;
		ps7_pl310_0: ps7-pl310@f8f02000 {
			arm,data-latency =  2 2>;
			arm,tag-latency = <2 2 2>;
			cache-level = <2>;
			cache-unified ;
			compatible = "xlnx,ps7-pl310-1.00.a", "arm,pl310-cache";
			interrupt-parent = <&ps7_scugic_0>;
			interrupts = <0 2 4>;
			reg = <0xf8f02000 0x1000>;
		} ;
		ps7_qspi_0: ps7-qspi@e000d000 {
			clock-names = "ref_clk", "aper_clk";
			clocks = <&clkc 10>, <&clkc 43>;
			compatible = "xlnx,ps7-qspi-1.00.a";
			interrupt-parent = <&ps7_scugic_0>;
			interrupts = <0 19 4>;
			is-dual = <0>;
			num-chip-select = <1>;
			reg = <0xe000d000 0x1000>;
			xlnx,fb-clk = <0x1>;
			xlnx,qspi-mode = <0x0>;
		} ;
		ps7_qspi_linear_0: ps7-qspi-linear@fc000000 {
			clock-names = "ref_clk", "aper_clk";
			clocks = <&clkc 10>, <&clkc 43>;
			compatible = "xlnx,ps7-qspi-linear-1.00.a";
			reg = <0xfc000000 0x1000000>;
		} ;
		ps7_ram_0: ps7-ram@0 {
			compatible = "xlnx,ps7-ram-1.00.a", "xlnx,ps7-ocm";
			interrupt-parent = <&ps7_scugic_0>;
			interrupts = <0 3 4>;
			reg = <0xfffc0000 0x40000>;
		} ;
		ps7_scuc_0: ps7-scuc@f8f00000 {
			compatible = "xlnx,ps7-scuc-1.00.a";
			reg = <0xf8f00000 0xfd>;
		} ;
		ps7_scugic_0: ps7-scugic@f8f01000 {
			#address-cells = <2>;
			#interrupt-cells = <3>;
			#size-cells = <1>;
			compatible = "xlnx,ps7-scugic-1.00.a", "arm,cortex-a9-gic", "arm,gic";
			interrupt-controller ;
			num_cpus = <2>;
			num_interrupts = <96>;
			reg = <0xf8f01000 0x1000>, <0xf8f00100 0x100>;
		} ;
		ps7_scutimer_0: ps7-scutimer@f8f00600 {
			clocks = <&clkc 4>;
			compatible = "xlnx,ps7-scutimer-1.00.a", "arm,cortex-a9-twd-timer";
			interrupt-parent = <&ps7_scugic_0>;
			interrupts = <1 13 0x301>;
			reg = <0xf8f00600 0x20>;
		} ;
		ps7_scuwdt_0: ps7-scuwdt@f8f00620 {
			clocks = <&clkc 4>;
			compatible = "xlnx,ps7-scuwdt-1.00.a";
			device_type = "watchdog";
			interrupt-parent = <&ps7_scugic_0>;
			interrupts = <1 14 0x301>;
			reg = <0xf8f00620 0xe0>;
		} ;
		ps7_sd_0: ps7-sdio@e0100000 {
			clock-frequency = <50000000>;
			clock-names = "ref_clk", "aper_clk";
			clocks = <&clkc 21>, <&clkc 32>;
			compatible = "xlnx,ps7-sdio-1.00.a", "generic-sdhci", "arasan,sdhci";
			interrupt-parent = <&ps7_scugic_0>;
			interrupts = <0 24 4>;
			reg = <0xe0100000 0x1000>;
			xlnx,has-cd = <0x1>;
			xlnx,has-power = <0x0>;
			xlnx,has-wp = <0x1>;
		} ;
		ps7_slcr_0: ps7-slcr@f8000000 {
			compatible = "xlnx,ps7-slcr-1.00.a", "xlnx,zynq-slcr";
			reg = <0xf8000000 0x1000>;
			clocks {
				#address-cells = <1>;
				#size-cells = <0>;
				clkc: clkc {
					#clock-cells = <1>;
					clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x",
						"cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci",
						"lqspi", "smc", "pcap", "gem0", "gem1",
						"fclk0", "fclk1", "fclk2", "fclk3", "can0",
						"can1", "sdio0", "sdio1", "uart0", "uart1",
						"spi0", "spi1", "dma", "usb0_aper", "usb1_aper",
						"gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper",
						"spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper",
						"uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper",
						"swdt", "dbg_trc", "dbg_apb";
					compatible = "xlnx,ps7-clkc";
					fclk-enable = <0xf>;
					ps-clk-frequency = <33333333>;
				} ;
			} ;
		} ;
		ps7_ttc_0: ps7-ttc@f8001000 {
			clocks = <&clkc 6>;
			compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc";
			interrupt-names = "ttc0", "ttc1", "ttc2";
			interrupt-parent = <&ps7_scugic_0>;
			interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
			reg = <0xf8001000 0x1000>;
		} ;
		ps7_uart_1: serial@e0001000 {
			clock-names = "ref_clk", "aper_clk";
			clocks = <&clkc 24>, <&clkc 41>;
			compatible = "xlnx,ps7-uart-1.00.a", "xlnx,xuartps";
			current-speed = <115200>;
			device_type = "serial";
			interrupt-parent = <&ps7_scugic_0>;
			interrupts = <0 50 4>;
			port-number = <1>;
			reg = <0xe0001000 0x1000>;
			xlnx,has-modem = <0x0>;
		} ;
		ps7_usb_0: ps7-usb@e0002000 {
			clocks = <&clkc 28>;
			compatible = "xlnx,ps7-usb-1.00.a";
			dr_mode = "host";
			interrupt-parent = <&ps7_scugic_0>;
			interrupts = <0 21 4>;
			phy_type = "ulpi";
			reg = <0xe0002000 0x1000>;
		} ;
		ps7_xadc: ps7-xadc@f8007100 {
			clocks = <&clkc 12>;
			compatible = "xlnx,ps7-xadc-1.00.a";
			interrupt-parent = <&ps7_scugic_0>;
			interrupts = <0 7 4>;
			reg = <0xf8007100 0x20>;
		} ;
	} ;
} ;

 

Tags (3)
0 Kudos
2 Replies
shabbirk
Moderator
Moderator
297 Views
Registered: ‎12-04-2016

Hi @bfung_2 

Can you check if TTC timer block along with the interrupts are enabled in the design and also check in the generated device tree if the entries are correctly generated?

Alternatively, you can try building the device tree outside the tool in case you are using any of the eval board and DTS files for the same are here for 14.7
https://github.com/Xilinx/linux-xlnx/tree/xilinx-v14.7/arch/arm/boot/dts

 

Regards

Shabbir

abhinayp
Xilinx Employee
Xilinx Employee
287 Views
Registered: ‎07-12-2018

Hi @bfung_2 ,

TTC interrupt baremetal code is available which is attached below, just try it out to rule out the issue.

https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/ttcps/examples/xttcps_intr_example.c

 

Best Regards
Abhinay PS
------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give kudos to a post which you think is helpful and reply oriented.
-------------------------------------------------------------------------------------------------------------------------------