I just discovered I could run Linux and Chipscope (JTAG) at the same time ( I have been doing this on the ZC706 so far).
This is a great feature because you actually debug the real design, this is no longer simulation.
Here is an example: program some registers (phase increment) from Linux, start a FSM, trigger on some signals.
I am not able to declare an interrupt while the logic analyzer is running: my guess is this device is using a hidden one so the FPGA-interrupt table is shifted by one. This means I cannot debug my IRQ handlers in this configuration.
I might be able to work it around in a near future.