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Observer ptg
Observer
2,047 Views
Registered: ‎05-07-2018

Mali 3D w/o DP PHY

SoC: UltraScale+ ZynqMP

 

I'm trying to get video stream from dp_video_out_pixel1[35:0], which will contain 3D graphics rendered by Mali GPU via X Window System app, into PL design.

The design has a customized PHY to drive MIPI-DSI display.

 

I don't need any DP PHY so I've turned off Display Port in ZynqMP's I/O Configuration but DRI2 had disappeared at the same time so X can't probe monitor.

 

Recently I've found pl_display DRM-compatible drivers in linux-xlnx which will be useful but I can't find any example applications which use it.

 

Questions are:

1. Can I get video stream into PL with 3D graphics enabled, without DP PHY?

2. Is PL Display Driver applicable to this case?

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15 Replies
Adventurer
Adventurer
1,990 Views
Registered: ‎12-02-2014

Re: Mali 3D w/o DP PHY

This is a highly requested feature, that as far as I can tell has not been addressed yet.

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Explorer
Explorer
1,985 Views
Registered: ‎02-16-2014

Re: Mali 3D w/o DP PHY

We should have a way to force it thru device-tree. Including EDID source/or plain resolution/timings.

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Observer ptg
Observer
1,977 Views
Registered: ‎05-07-2018

Re: Mali 3D w/o DP PHY

Okay, finally I did it. But it was not straightforward. (3D availability is not checked yet. I'll post the result here next week)

 

I've configured MPSoC as follows:

  • DisplayPort enabled
  • EMIO output (No physical output pin)
  • No Lanes (= No PSGTR)
  • Custom MIPI PHY

 

My linux env is as follows:

  • Debian 9 Stretch
  • Device tree built on Xilinx SDK, customized a bit
  • BOOT.BIN (Bitstream from Vivado 2018.2, PMU + FSBL built on Xilinx SDK, U-Boot which is built from source)
  • Linux Kernel (Tag: xilinx-v2018.2)

 

I've done printk-debug in `zynqmp-dpsub` which provides DRM and DRI. The steps which cause failure of DRM init is like:

  1. Linux probes DP subsystem and enters into zynqmp_dpsub_probe .
  2. zynqmp_dpsub_probe calls zynqmp_dp_probe , implemented in zynqmp_dp.c , to initialize DP PHY.
  3. Of course there's no PHY so devm_get_phy fails , and then it postpones probing
  4. :P

 

I'm happy to introduce that this problem is already fixed in master branch. The next Vivado release, 2018.3, will have fixed implementation. I've never found that fix until I write this post.

 

As a quick fix, I commented out the lines which are related to PHY initialization, roughly between Line 1793 - Line 1818 . I hope it's useful when you have to use xilinx-v2018.2 branch instead of bleeding-edge master.

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Observer ptg
Observer
1,973 Views
Registered: ‎05-07-2018

Re: Mali 3D w/o DP PHY

Setting new resolution was achieved by xrandr and/or xorg.conf.

I have LXDE as a desktop env so my solution is that setting custom script which runs xrandr, on init of LightDM.

 

I've also got fbcon by adding `video=DP-1:640x480e` in cmdline.j

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Explorer
Explorer
1,956 Views
Registered: ‎02-16-2014

Re: Mali 3D w/o DP PHY

I'm happy to introduce that this problem is already fixed in master branch. The next Vivado release, 2018.3, will have fixed implementation. I've never found that fix until I write this post.

Can't find? Can you post a commit number?

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Explorer
Explorer
1,949 Views
Registered: ‎02-16-2014

Re: Mali 3D w/o DP PHY

Also, are you using "old" or "new" driver?

 

http://www.wiki.xilinx.com/ZynqMP%20DisplayPort%20Linux%20driver

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Observer ptg
Observer
1,928 Views
Registered: ‎05-07-2018

Re: Mali 3D w/o DP PHY

The commit is here.

The driver is the new one of course. Xilinx had dropped their old DRM driver (xilinx) since 2018.1 and replaced to the new one (xlnx). Search for zynqmp-display.

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Explorer
Explorer
1,862 Views
Registered: ‎02-16-2014

Re: Mali 3D w/o DP PHY

Can't make it to work with new driver.

Can you please share your device-tree DP related nodes?

 

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Observer shinya
Observer
1,584 Views
Registered: ‎08-31-2017

Re: Mali 3D w/o DP PHY

Did you use "PL Display Driver"?

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Observer ptg
Observer
1,553 Views
Registered: ‎05-07-2018

Re: Mali 3D w/o DP PHY

The custom DT doesn't modify nodes related to DP and DRM. Please ignore it. I'm using the DT which Xilinx SDK generated. Nothing special stuff here.

 

I just enabled DP in Vivado block design and applied the drive patch I mentioned before.

 

                zynqmp-display@fd4a0000 {
                        compatible = "xlnx,zynqmp-dpsub-1.7";
                        status = "okay";
                        reg = <0x0 0xfd4a0000 0x0 0x1000 0x0 0xfd4aa000 0x0 0x1000 0x0 0xfd4ab000 0x0 0x1000 0x0 0xfd4ac000 0x0 0x1000>;
                        reg-names = "dp", "blend", "av_buf", "aud";
                        interrupts = <0x0 0x77 0x4>;
                        interrupt-parent = <0x4>;
                        clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in";
                        power-domains = <0x2a>;
                        clocks = <0x2b 0x3 0x11 0x3 0x10>;

                        vid-layer {
                                dma-names = "vid0", "vid1", "vid2";
                                dmas = <0x2c 0x0 0x2c 0x1 0x2c 0x2>;
                        };

                        gfx-layer {
                                dma-names = "gfx0";
                                dmas = <0x2c 0x3>;
                        };

                        i2c-bus {
                        };

                        zynqmp_dp_snd_codec0 {
                                compatible = "xlnx,dp-snd-codec";
                                clock-names = "aud_clk";
                                clocks = <0x3 0x11>;
                                status = "okay";
                                linux,phandle = <0x2f>;
                                phandle = <0x2f>;
                        };

                        zynqmp_dp_snd_pcm0 {
                                compatible = "xlnx,dp-snd-pcm";
                                dmas = <0x2c 0x4>;
                                dma-names = "tx";
                                status = "okay";
                                linux,phandle = <0x2d>;
                                phandle = <0x2d>;
                        };

                        zynqmp_dp_snd_pcm1 {
                                compatible = "xlnx,dp-snd-pcm";
                                dmas = <0x2c 0x5>;
                                dma-names = "tx";
                                status = "okay";
                                linux,phandle = <0x2e>;
                                phandle = <0x2e>;
                        };

                        zynqmp_dp_snd_card {
                                compatible = "xlnx,dp-snd-card";
                                xlnx,dp-snd-pcm = <0x2d 0x2e>;
                                xlnx,dp-snd-codec = <0x2f>;
                                status = "okay";
                        };
                };
        };

`zynqmp-display` node will have `max-lanes` as its property but it doesn't. It's because the lanes are disabled.

 

Screenshot from 2018-07-26 13-52-20.png

 

@fanat9 
>> Can't make it to work with new driver.

What is your problem? The stack related to DP is huge. You may failed to initiate your logic, unresolved timing errors, noisy signal, lack of xf86-video-armsoc, broken xorg.conf, and more.

Explorer
Explorer
1,537 Views
Registered: ‎02-16-2014

Re: Mali 3D w/o DP PHY

Looks like adding "e" flag to cmd line did the trick!

 

I did try it before, but something else must be misconfigured or something. Anyway, I'm all set.

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Observer ptg
Observer
1,488 Views
Registered: ‎05-07-2018

Re: Mali 3D w/o DP PHY

I backported the fix in master branch which I mentioned before but it was not what I expected. This does fix the PHY initialization bug, but the CRTC disappears so we can't have any (virtual) plane. I guess it's because Xilinx wants us to connect their IP like Video Mixer to pixel output and write a node in device tree.

 

At present we don't have any way to make a virtual CRTC. Is there any solution to have a plane/CRTC without having Video Mixer in PL?

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Observer ema1905
Observer
1,309 Views
Registered: ‎03-29-2012

Re: Mali 3D w/o DP PHY

I'm tryng to do the same thing :

  • DisplayPort enabled
  • EMIO output (No physical output pin)
  • No Lanes (= No PSGTR)
  • Custom output to PL

I've applied the commit mentionet before in config:

CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_REMOTE_DOWNLOAD_PATH="git://github.com/Xilinx/linux-xlnx.git;protocol=https"
CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_REMOTE_REFERENCE="99c43ab5afc0717cd6bace1a8667df2badc7b082"

 

But if i enable the zynqmp_dpsub: zynqmp-display@fd4a0000 in the device tree:

&zynqmp_dpsub {
    status = "okay";
};

 

The kernel hang after ZynqMP DMA driver Probe success without any error.

could you help me?

Thank you

 

 

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Observer ema1905
Observer
1,295 Views
Registered: ‎03-29-2012

Re: Mali 3D w/o DP PHY

I go  ahead on my project but i created a post to follow on:

https://forums.xilinx.com/t5/Embedded-Linux/DP-Display-Port-Live-video-to-PL/m-p/896374#M29143

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