Hello
I am running Petalinux 2017.4 on a Zynq MPSOC APU. I have a number of AXI slave devices in programmable logic that are connected to the PS through one of the PS-PL AXI interfaces.
I am using the UIO platform driver ("generic-uio") to successfully read and write from these AXI slaves:
m_ipAxiRegister = open(cUioFileName, O_RDWR);
m_pAxiRegister = mmap(NULL, AXI_REGISTER_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, m_ipAxiRegister, 0);
// Writing to register
*((unsigned *)(((uint8_t*)m_pAxiRegister) + (uAddress * 4))) = uWriteData;
// Reading from register
unsigned uReadWord = *((unsigned *)(((uint8_t*)m_pAxiRegister) + (uAddress * 4)));
Generally with Linux device drivers you need to use memory barriers (mb(), rmb(), wmb()) to ensure that accesses to hardware actually happen when you expect and that order is maintained. Our AXI slaves in programmable logic rely on order being maintained in reads and writes.
However I can't seem to find out two very important pieces of information after searching various forums for an answer:
1) Does the UIO platform driver need memory barriers? Or can I assume that writes to memory and reads from memory are performed in the order they are executed in the user application?
2) My initial assessment of this is that I have had to turn off all compiler optimisations in Xilinx SDK to ensure that the reads and writes happen in the order expected. However, there must be a better way to do this so that only the order of the accesses to the device hardware is maintained and the rest of the application software can be optimised as the compiler sees fit.
How do I force the AXI writes to complete and all AXI reads to be up to data for my AXI slaves in programmable logicin a Xilinx SDK user space Linux application? Does the UIO platform driver do this for me?
Thank you.
