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Voyager
Voyager
5,529 Views
Registered: ‎09-14-2016

Nand driver S34ML02G100BHI000

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Hi all,

 

I'm currently working with a custom board based on Zynq7030 and i have some trouble with NAND driver.

 

I have created a custom recipe under Yocto based on meta-xilinx, NAND driver is activated and we are able to read/write from u-boot-xlnx loaded from JTAG. But we have this error during kernel boot:

 

nand: No NAND device found
pl35x-nand e1000000.flash: nand_scan_ident for NAND failed

For info the ref NAND is : S34ML02G100BHI000

Kernel : Linux version 4.6.0-xilinx

The driver seems to be correctly loaded but we have nothing in /dev 

 

All suggestions are welcome :-)

Trigger

 

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Voyager
Voyager
3,661 Views
Registered: ‎09-14-2016

Re: Nand driver S34ML02G100BHI000

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Hi @derekparks,

 

Yes, I can explain a little bit. The trouble was linked to our custom hardware, with NAND we have to respect timing and printed circuit must be designed with propagation time...

 

I'm not sure to be really clear, but if you have different conductive trace you have to set correctly timing in Vivado AND in your device-tree also:

 

&nand0 {
    arm,nand-cycle-t0 = <0x3>;
    arm,nand-cycle-t1 = <0x3>;
    arm,nand-cycle-t2 = <0x2>;
    arm,nand-cycle-t3 = <0x2>;
    arm,nand-cycle-t4 = <0x2>;
    arm,nand-cycle-t5 = <0x1>;
    arm,nand-cycle-t6 = <0x3>;
    status = "okay";

    partition@nand-fsbl-uboot {
        label = "nand-fsbl-uboot";
        reg = <0x0 0x100000>;
    };
    partition@nand-linux {
        label = "nand-linux";
        reg = <0x100000 0x500000>;
    };
    partition@nand-device-tree {
        label = "nand-device-tree";
        reg = <0x600000 0x20000>;
    };
    partition@nand-rootfs {
        label = "nand-rootfs";
        reg = <0x620000 0x5E0000>;
    };
    partition@nand-bitstream {
        label = "nand-bitstream";
        reg = <0xC00000 0x400000>;
    };

 

Edit:

 

 

Device-tree settings:

The timing parameters t0, t1, t2, t3, t4, t5, t6 denotes
nand-cycle-t0 : Read cycle time(t_rc).
nand-cycle-t1 : Write cycle time(t_wc).
nand-cycle-t2 : re_n assertion delay(t_rea).
nand-cycle-t3 : we_n de-assertion delay(t_wp).
nand-cycle-t4 : Status read time(t_clr)
nand-cycle-t5 : ID read time(t_ar)
nand-cycle-t6 : busy to re_n(t_rr)

 

For our custom design, we had to update timing up to:

 

 

    arm,nand-cycle-t0 = <0x4>; /* t_rc  */
    arm,nand-cycle-t1 = <0x4>; /* t_wc  */
    arm,nand-cycle-t2 = <0x1>; /* t_rea */
    arm,nand-cycle-t3 = <0x2>; /* t_wp  */
    arm,nand-cycle-t4 = <0x2>; /* t_clr */
    arm,nand-cycle-t5 = <0x2>; /* t_ar  */
    arm,nand-cycle-t6 = <0x4>; /* t_rr  */

 

Cheers,

Trigger 

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17 Replies
Community Manager
Community Manager
5,523 Views
Registered: ‎07-23-2012

Re: Nand driver S34ML02G100BHI000

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Are you able to run the bare metal driver successfully? The error message states that the part was not identified.

Checking the baremetal drivers helps in making sure that the interface was correct.
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Voyager
Voyager
5,523 Views
Registered: ‎09-14-2016

Re: Nand driver S34ML02G100BHI000

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The FLASH is supported by Zynq as reported in AR#50991 for sure :)

 

More informations about NAND definition:

* zynq-7000.dtsi

		smcc: memory-controller@e000e000 {
			#address-cells = <1>;
			#size-cells = <1>;
			status = "disabled";
			clock-names = "memclk", "aclk";
			clocks = <&clkc 11>, <&clkc 44>;
			compatible = "arm,pl353-smc-r2p1";
			interrupt-parent = <&intc>;
			interrupts = <0 18 4>;
			ranges ;
			reg = <0xe000e000 0x1000>;
			nand0: flash@e1000000 {
				status = "disabled";
				compatible = "arm,pl353-nand-r2p1";
				reg = <0xe1000000 0x1000000>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;
			};
			nor0: flash@e2000000 {
				status = "disabled";
				compatible = "cfi-flash";
				reg = <0xe2000000 0x2000000>;
				#address-cells = <1>;
				#size-cells = <1>;
			};
		};

* custom-zynq.dts

 

&nand0 {
    arm,nand-cycle-t0 = <0x3>;
    arm,nand-cycle-t1 = <0x3>;
    arm,nand-cycle-t2 = <0x2>;
    arm,nand-cycle-t3 = <0x2>;
    arm,nand-cycle-t4 = <0x2>;
    arm,nand-cycle-t5 = <0x1>;
    arm,nand-cycle-t6 = <0x3>;
    status = "okay";

    partition@nand-fsbl-uboot {
        label = "nand-fsbl-uboot";
        reg = <0x0 0x100000>;
    };
    partition@nand-linux {
        label = "nand-linux";
        reg = <0x100000 0x500000>;
    };
    partition@nand-device-tree {
        label = "nand-device-tree";
        reg = <0x600000 0x20000>;
    };
    partition@nand-rootfs {
        label = "nand-rootfs";
        reg = <0x620000 0x5E0000>;
    };
    partition@nand-bitstream {
        label = "nand-bitstream";
        reg = <0xC00000 0x400000>;
    };
};
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Voyager
Voyager
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Registered: ‎09-14-2016

Re: Nand driver S34ML02G100BHI000

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I didn't test the bare metal driver because u-boot-xlnx is able to access, i will do it :)

 

Thx for info

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Voyager
Voyager
5,501 Views
Registered: ‎09-14-2016

Re: Nand driver S34ML02G100BHI000

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Ok so after testing everything seems good:

Nand Flash Read Write Example Test
Successfully ran Nand Flash Read Write Example TesT
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Voyager
Voyager
5,425 Views
Registered: ‎09-14-2016

Re: Nand driver S34ML02G100BHI000

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More information today: we are able to program NAND flash from SDK successfully but we have trouble with u-boot driver 

 

Any clue or advice ?

 

Cheers,

Trigger

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Community Manager
Community Manager
5,322 Views
Registered: ‎07-23-2012

Re: Nand driver S34ML02G100BHI000

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Can you please elaborate the issue you see with u-boot driver?
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Voyager
Voyager
5,189 Views
Registered: ‎09-14-2016

Re: Nand driver S34ML02G100BHI000

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First I apologise for taking so long in responding to question i was out of office.

 

So i don't have issue with u-boot driver:

 

U-Boot 2016.01 (Jan 23 2017 - 11:40:11 +0100)

Model: Bullseye Board
Board: Xilinx Zynq
DRAM:  ECC disabled 1 GiB
NAND:  256 MiB
*** Warning - bad CRC, using default environment

In:    serial@e0000000
Out:   serial@e0000000
Err:   serial@e0000000
Model: Bullseye Board
Board: Xilinx Zynq
Hit any key to stop autoboot:  0
Copying Custom Linux from NAND flash to RAM :-)...

NAND read: device 0 offset 0x100000, size 0x3b2e08
 3878408 bytes read: OK

NAND read: device 0 offset 0x600000, size 0x26d3
 9939 bytes read: OK
Copying ramdisk...

NAND read: device 0 offset 0x800000, size 0xac27f2
 11282418 bytes read: OK
k: 0x03A00000 r: 0x02000000 d: 0x03900000
## Booting kernel from Legacy Image at 03a00000 ...
   Image Name:   Linux-4.6.0-xilinx-22285-g0e4e40
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    3878344 Bytes = 3.7 MiB
   Load Address: 00008000
   Entry Point:  00008000
   Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 02000000 ...
   Image Name:   core-image-bullseye
   Image Type:   ARM Linux RAMDisk Image (gzip compressed)
   Data Size:    11282354 Bytes = 10.8 MiB
   Load Address: 00000000
   Entry Point:  00000000
   Verifying Checksum ... OK
## Flattened Device Tree blob at 03900000
   Booting using the fdt blob at 0x3900000
   Loading Kernel Image ... OK
   Using Device Tree in place at 03900000, end 039056d2

Starting kernel ...

Booting Linux on physical CPU 0x0
[...]

but i'm stuck now on the Linux Driver part...

 

If someone has already use this NAND please feel free to share :)

 

Thx.

Trigger

 

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Moderator
Moderator
5,184 Views
Registered: ‎12-04-2016

Re: Nand driver S34ML02G100BHI000

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Hi

 

May I know why are you suspecting NAND issue, instead it would be problem with DDR i assume. Did u run mtest on U-boot and was DDR fine?

 

I mean if you miss DDR training parameters, you will face this kind of issue.

 

Try enabling earlyprintk in kernel and see what is happening next?

 

 

Best Regards

Shabbir

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Voyager
Voyager
5,178 Views
Registered: ‎09-14-2016

Re: Nand driver S34ML02G100BHI000

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Hi,

 

Thank you for the quick reply.

 

Could you explain me why the RAM could be wrong ? What is the link between RAM and NAND driver ?

 

I'm following your advice :

 

U-boot> mw 0x1000 0x55AA55AA 0x40
U-boot> md 0x1000 0x40
00001000: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
00001010: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
00001020: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
00001030: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
00001040: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
00001050: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
00001060: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
00001070: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
00001080: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
00001090: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
000010a0: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
000010b0: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
000010c0: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
000010d0: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
000010e0: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
000010f0: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U

U-boot> nand erase 0 0x10000

NAND erase: device 0 offset 0x0, size 0x10000
Erasing at 0x0 -- 100% complete.
OK


U-boot> nand write 0x1000 0 0x10000

NAND write: device 0 offset 0x0, size 0x10000
 65536 bytes written: OK

U-boot> nand read 0x2000 0 0x1000

NAND read: device 0 offset 0x0, size 0x1000
 4096 bytes read: OK
U-boot> md 0x2000
00002000: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
00002010: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
00002020: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
00002030: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
00002040: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
00002050: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
00002060: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
00002070: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
00002080: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
00002090: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
000020a0: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
000020b0: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
000020c0: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
000020d0: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
000020e0: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U
000020f0: 55aa55aa 55aa55aa 55aa55aa 55aa55aa    .U.U.U.U.U.U.U.U

U-boot> cmp 0x1000 0x2000 0x40
Total of 64 word(s) were the same

and mtest is still running:

 

Zynq-Bulls> mtest
Testing 00000000 ... 00001000:
Pattern 00000000  Writing...  Reading.. Iteration:  64241
Pattern FFFFFFFF  Writing...  Reading.. Iteration: 153726    Reading...Iteration:  65535

 

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Moderator
Moderator
4,205 Views
Registered: ‎04-17-2011

Re: Nand driver S34ML02G100BHI000

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In your DT, the SMC controller status shows as disabled:

smcc: memory-controller@e000e000 {
			#address-cells = <1>;
			#size-cells = <1>;
			status = "disabled";

How about adding an entry in custom dts as

@smcc {

             status = "okay";

            };

 

Also, do cross check if the following Kernel configs are enabled:


Device Drivers -> Memory Technology Device (MTD) support -> NAND Device Support ->ARM PL35X NAND flash driver

CONFIG_MTD_NAND = y
CONFIG_ARM = y
CONFIG_PL35X_SMC = y
CONFIG_MTD_NAND_PL35X = y 

Regards,
Debraj
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Voyager
Voyager
4,159 Views
Registered: ‎09-14-2016

Re: Nand driver S34ML02G100BHI000

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hi,

 

Thx for informations,

 

I change the DT status for okay but the same issue appeared.

 

[edit]: After tweaking a little bit driver sources :

 

nand: device found, Manufacturer ID: 0x01, Chip ID: 0xda
nand: AMD/Spansion NAND 256MiB 3,3V 8-bit
nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64

pl35x_nand_cmd_function timed out
pl35x_nand_cmd_function timed out
pl35x_nand_cmd_function timed out
pl35x_nand_cmd_function timed out
Bad block table not found for chip 0
pl35x_nand_cmd_function timed out
pl35x_nand_cmd_function timed out
pl35x_nand_cmd_function timed out
pl35x_nand_cmd_function timed out
Bad block table not found for chip 0
Scanning device for bad blocks
pl35x_nand_cmd_function timed out
Bad eraseblock 0 at 0x000000000000
pl35x_nand_cmd_function timed out
Bad eraseblock 1 at 0x000000020000
pl35x_nand_cmd_function timed out
Bad eraseblock 2 at 0x000000040000

[...]
Bad eraseblock 2046 at 0x00000ffc0000
pl35x_nand_cmd_function timed out
Bad eraseblock 2047 at 0x00000ffe0000
No space left to write bad block table
nand_bbt: error while writing bad block table -28
pl35x-nand e1000000.flash: nand_scan_tail for NAND failed

And i'm still stuck :(

 

Regards,

Nicolas.

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Participant shrtique
Participant
2,945 Views
Registered: ‎08-22-2016

Re: Nand driver S34ML02G100BHI000

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Hello, I want to up the thread, cuz I have the same problem but with S34ML04G1.

 

So, did you solve the problem?

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Voyager
Voyager
2,916 Views
Registered: ‎09-14-2016

Re: Nand driver S34ML02G100BHI000

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Hi,

 

Yes the problem is solved now, sorry for not posting the solution :(

The trouble was in NAND timings.

 

Feel free to attach some info about your trouble (it's maybe a little different)

 

Regards,

Trigger

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Observer derekparks
Observer
2,408 Views
Registered: ‎09-14-2017

Re: Nand driver S34ML02G100BHI000

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Can you elaborate more on the NAND timings solution?
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Voyager
Voyager
3,662 Views
Registered: ‎09-14-2016

Re: Nand driver S34ML02G100BHI000

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Hi @derekparks,

 

Yes, I can explain a little bit. The trouble was linked to our custom hardware, with NAND we have to respect timing and printed circuit must be designed with propagation time...

 

I'm not sure to be really clear, but if you have different conductive trace you have to set correctly timing in Vivado AND in your device-tree also:

 

&nand0 {
    arm,nand-cycle-t0 = <0x3>;
    arm,nand-cycle-t1 = <0x3>;
    arm,nand-cycle-t2 = <0x2>;
    arm,nand-cycle-t3 = <0x2>;
    arm,nand-cycle-t4 = <0x2>;
    arm,nand-cycle-t5 = <0x1>;
    arm,nand-cycle-t6 = <0x3>;
    status = "okay";

    partition@nand-fsbl-uboot {
        label = "nand-fsbl-uboot";
        reg = <0x0 0x100000>;
    };
    partition@nand-linux {
        label = "nand-linux";
        reg = <0x100000 0x500000>;
    };
    partition@nand-device-tree {
        label = "nand-device-tree";
        reg = <0x600000 0x20000>;
    };
    partition@nand-rootfs {
        label = "nand-rootfs";
        reg = <0x620000 0x5E0000>;
    };
    partition@nand-bitstream {
        label = "nand-bitstream";
        reg = <0xC00000 0x400000>;
    };

 

Edit:

 

 

Device-tree settings:

The timing parameters t0, t1, t2, t3, t4, t5, t6 denotes
nand-cycle-t0 : Read cycle time(t_rc).
nand-cycle-t1 : Write cycle time(t_wc).
nand-cycle-t2 : re_n assertion delay(t_rea).
nand-cycle-t3 : we_n de-assertion delay(t_wp).
nand-cycle-t4 : Status read time(t_clr)
nand-cycle-t5 : ID read time(t_ar)
nand-cycle-t6 : busy to re_n(t_rr)

 

For our custom design, we had to update timing up to:

 

 

    arm,nand-cycle-t0 = <0x4>; /* t_rc  */
    arm,nand-cycle-t1 = <0x4>; /* t_wc  */
    arm,nand-cycle-t2 = <0x1>; /* t_rea */
    arm,nand-cycle-t3 = <0x2>; /* t_wp  */
    arm,nand-cycle-t4 = <0x2>; /* t_clr */
    arm,nand-cycle-t5 = <0x2>; /* t_ar  */
    arm,nand-cycle-t6 = <0x4>; /* t_rr  */

 

Cheers,

Trigger 

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Observer derekparks
Observer
2,376 Views
Registered: ‎09-14-2017

Re: Nand driver S34ML02G100BHI000

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Super helpful Trigger, thanks.  Can you post the top-level nand0 device tree settings that you referenced in your snippet? 

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Voyager
Voyager
2,369 Views
Registered: ‎09-14-2016

Re: Nand driver S34ML02G100BHI000

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yep sure @derekparks

 

It's the basic file taken from xilinx repo :) -> https://github.com/Xilinx/linux-xlnx/blob/master/arch/arm/boot/dts/zynq-7000.dtsi

 

		smcc: memory-controller@e000e000 {
			#address-cells = <1>;
			#size-cells = <1>;
			status = "disabled";
			clock-names = "memclk", "aclk";
			clocks = <&clkc 11>, <&clkc 44>;
			compatible = "arm,pl353-smc-r2p1";
			interrupt-parent = <&intc>;
			interrupts = <0 18 4>;
			ranges ;
			reg = <0xe000e000 0x1000>;
			nand0: flash@e1000000 {
				status = "disabled";
				compatible = "arm,pl353-nand-r2p1";
				reg = <0xe1000000 0x1000000>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;
			};
			nor0: flash@e2000000 {
				status = "disabled";
				compatible = "cfi-flash";
				reg = <0xe2000000 0x2000000>;
				#address-cells = <1>;
				#size-cells = <1>;
			};
		};

 

Cheers,

Trigger

 

 

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