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dfs
Observer
Observer
737 Views
Registered: ‎10-10-2018

Petalinux 2019.2 FSBL compilation failure with axipcie

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Hi,

I've been given an .xsa file for our board that includes an NVMe and PCIe IP.  When I try to build Petalinux images, the FSBL compilation fails with the following errors:

Compiling axipcie
| xdmapcie_g.c:42:38: error: 'XPAR_XDMAPCIE_NUM_INSTANCES' undeclared here (not in a function); did you mean 'XPAR_XEMACPS_NUM_INSTANCES'?
| XDmaPcie_Config XDmaPcie_ConfigTable[XPAR_XDMAPCIE_NUM_INSTANCES] =
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
| XPAR_XEMACPS_NUM_INSTANCES
| xdmapcie_g.c:45:3: error: 'XPAR_XDMA_0_DEVICE_ID' undeclared here (not in a function); did you mean 'XPAR_XZDMA_0_DEVICE_ID'?
| XPAR_XDMA_0_DEVICE_ID,
| ^~~~~~~~~~~~~~~~~~~~~
| XPAR_XZDMA_0_DEVICE_ID
| xdmapcie_g.c:46:3: error: 'XPAR_XDMA_0_BASEADDR' undeclared here (not in a function); did you mean 'XPAR_XZDMA_0_BASEADDR'?
| XPAR_XDMA_0_BASEADDR,

and a bunch more similar.  I cannot find those identifiers anywhere.  Is xparameters.h somehow being generated incorrectly?  The .XSA file was generated by an FPGA designer using Vivado 2019.2.

Regards,

Dianne

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katsuki
Xilinx Employee
Xilinx Employee
697 Views
Registered: ‎11-05-2019

 

Hello @dfs 

 

What is the PCIe IP instance name on your Block Design?

Could you try resetting the PCIe IP instance name to the default?

 

Thank you


Ka2ki
Don't forget to reply, kudo, and accept as solution.


Don’t forget to reply, kudo, and accept as solution. If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs

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3 Replies
katsuki
Xilinx Employee
Xilinx Employee
698 Views
Registered: ‎11-05-2019

 

Hello @dfs 

 

What is the PCIe IP instance name on your Block Design?

Could you try resetting the PCIe IP instance name to the default?

 

Thank you


Ka2ki
Don't forget to reply, kudo, and accept as solution.


Don’t forget to reply, kudo, and accept as solution. If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs

View solution in original post

dfs
Observer
Observer
660 Views
Registered: ‎10-10-2018

Hello,

Our FPGA designer made the change you suggested, and it fixed the compilation problem.  Thank you very much!

Regards,

Dianne.

 

katsuki
Xilinx Employee
Xilinx Employee
637 Views
Registered: ‎11-05-2019

 

Hello @dfs 

 

Thanks for your reply.

Could you please kudo, and accept as solution.

 

Thank you

Ka2ki


Don’t forget to reply, kudo, and accept as solution. If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
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