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Explorer
Explorer
3,900 Views
Registered: ‎05-22-2008

Petalinux driver/module for custom AXI-Lite IP

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I am getting my embedded linux system up and running on a ZCU102 board. I used petalinux with the reference BSP and got my linux up and running. I added an echo server application. It works. 

 

I then went back to Vivado, added an custom peripheral for which the CPU interface is an AXI4-Lite Slave. Connected, generated a bit stream, exported the HW.

 

I go back to petalinux, rerun petalinux-config --get-hw-description..

 

Now:

 

in pl.dtsi I see my peripheral...Great

 

in <proj-dir>project-spec/hw-description/drivers/ there is the driver code that Vivado created for my peripheral.

 

I didn't modify the driver at all, so it basically consists of calls to Xil_In32 and Xil_Out32

 

I don't know exactly what I need to do right now. I find my self wanting to just include the header in my application, but when I tried that, compilation of my application failed, because it couldn't find the header. But, even if I could direct it to the header, I feel like that should fail because to talk to hardware I need to make system calls via exposed functions in a kernel module.

 

But if that is the case, then what is the point of the driver that Vivado compiles and Petalinux imports? Do I need to adapt the Driver into a module? I briefly read about using the Userspace IO module, but that seems to not use the Xil_In32 and Xil_Out32 calls.

 

I guess what I'm trying to figure out is, I added a custom peripheral to my hardware, with an AXI4-Lite Slave interface. I then imported said hardware into my petalinux project. What do I need to do now?

Does petalinux automagically create and include the appropriate ko module?

Do I need to create a ko module? from Scratch? or Start with the driver that was imported? or is the driver only really useful for bare-metal use cases?

 

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Moderator
Moderator
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Registered: ‎09-12-2007

The tools will create a Baremetal driver that uses the API that you mentioned in the standalone BSP and is not applicable in Linux

If you want to create a driver, I would use the UIO driver as a stating point.

http://www.wiki.xilinx.com/Testing+UIO+with+Interrupt+on+Zynq+Ultrascale

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Moderator
Moderator
4,041 Views
Registered: ‎09-12-2007

The tools will create a Baremetal driver that uses the API that you mentioned in the standalone BSP and is not applicable in Linux

If you want to create a driver, I would use the UIO driver as a stating point.

http://www.wiki.xilinx.com/Testing+UIO+with+Interrupt+on+Zynq+Ultrascale

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Explorer
Explorer
3,857 Views
Registered: ‎05-22-2008

thanks stephenm,

 

I have it working with linux seeing my IP as a UIO device, and then I use mmap to get access to the registers. I'm going to have to think about how I want to use this setup, and my first thought is, do any of the AXI IP have prebuilt kernel modules/drivers? 

 

I'm thinking about how my design in the PL will interface to the PS, and I will likely have an AXI Stream Fifo with the PS on one side and custom logic on the other side. 

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Explorer
Explorer
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Registered: ‎05-22-2008

So, I've made some headway answering my own question.

 

http://www.wiki.xilinx.com/Linux%20Drivers

 

It looks like what I'm looking for is likely one of the axi_dma drivers.

 

Also,

 

the below post appears to show usage/control of the axi_dma block using mm'ed IO.

 

https://lauri.xn--vsandi-pxa.com/hdl/zynq/xilinx-dma.html

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Observer
Observer
1,502 Views
Registered: ‎11-23-2018
Hi @mckinjo4,
have you figured out the solution? I have similar issue and am trying to come up with a solution (please see my post):

https://forums.xilinx.com/t5/Memory-Interfaces-and-NoC/AXI-Interconnect-PS-PL-on-Zynq-US/m-p/1055623

Best regards
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