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Contributor
Contributor
6,380 Views
Registered: ‎05-27-2009

Problem running XAPP1129 on a ML405 under EDK9.2

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Based upon my previous success using MPMC on the ML405 I expected XAPP 1129 to run without much effort. OK I'm a dreamer! Instead, I get the message

 

Command Line: platgen -p xc4vfx20ff672-10 -lang vhdl -lp
/home/flash/opt/Xil_Proj/ -lp /home/flash/opt/Xil_Proj/user_ip/ -lp
/home/flash/opt/Xil_GPR/ system.mhs
Parse system.mhs ...
Read MPD definitions ...
ERROR:MDT - IPNAME:xps_ll_example INSTANCE:xps_ll_example_0 -
   /home/flash/opt/Xil_Proj/ML405/base_3/system.mhs line 277 - not supported for
   architecture 'virtex4fx'!
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
make: *** [implementation/ppc405_0_wrapper.ngc] Error 2
ERROR:MDT - platgen failed with errors!

 

when I try to generate a netlist.

 

I've attached the bits from the .mhs file and the .mpd file that might in any way be relevant.

 

Oh... What to do? Anyone got a clue they could toss my way?

 

 
BEGIN mpmc
 PARAMETER INSTANCE = DDR_SDRAM
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_NUM_PORTS = 4
 PARAMETER C_MEM_PARTNO = HYB25D512160BE-5
 PARAMETER C_MEM_DATA_WIDTH = 32
 PARAMETER C_MEM_TYPE = DDR
 PARAMETER C_NUM_IDELAYCTRL = 2
 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y2
 PARAMETER C_PIM1_BASETYPE = 2
 PARAMETER C_PIM2_BASETYPE = 3
 PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
 PARAMETER C_SDMA2_PI2LL_CLK_RATIO = 1
 PARAMETER C_MPMC_BASEADDR = 0x00000000
 PARAMETER C_MPMC_HIGHADDR = 0x07FFFFFF
 PARAMETER C_SDMA_CTRL_BASEADDR = 0x84600000
 PARAMETER C_SDMA_CTRL_HIGHADDR = 0x8460FFFF
 PARAMETER C_PIM3_BASETYPE = 3
 PARAMETER C_SDMA3_PI2LL_CLK_RATIO = 1
 BUS_INTERFACE SPLB0 = ppc405_0_iplb1
 BUS_INTERFACE SPLB1 = ppc405_0_dplb1
 BUS_INTERFACE SDMA_LL2 = TriMode_MAC_GMII_LLINK0
 BUS_INTERFACE SDMA_CTRL2 = plb
 BUS_INTERFACE SDMA_CTRL3 = plb
 BUS_INTERFACE SDMA_LL3 = xps_ll_example_0_LLINK0
 PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr
 PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr
 PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n
 PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE
 PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n
 PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n
 PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n
 PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM
 PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS
 PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ
 PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk
 PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n
 PORT MPMC_Clk0 = sys_clk_s
 PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s
 PORT SDMA2_Clk = sys_clk_s
 PORT MPMC_Clk_200MHz = clk_200mhz_s
 PORT MPMC_Rst = sys_bus_reset
 PORT SDMA2_Rx_IntOut = DDR_SDRAM_SDMA2_Rx_IntOut
 PORT SDMA2_Tx_IntOut = DDR_SDRAM_SDMA2_Tx_IntOut
END

 

BEGIN xps_ll_example
 PARAMETER INSTANCE = xps_ll_example_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_INCLUDE_DPHASE_TIMER = 1
 BUS_INTERFACE LLINK0 = xps_ll_example_0_LLINK0
 BUS_INTERFACE SPLB = plb
 PORT Ll_Rst = sys_bus_reset
 PORT Ll_Clk = sys_clk_s
END

 

BEGIN xps_ll_example
 
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION ARCH_SUPPORT_MAP = (OTHERS=DEVELOPMENT)
OPTION IP_GROUP = MICROBLAZE:PPC:USER
OPTION DESC = XPS_LL_EXAMPLE
OPTION STYLE = MIX
OPTION RUN_NGCBUILD = TRUE
 
 
## Bus Interfaces
BUS_INTERFACE BUS = SPLB, BUS_TYPE = SLAVE, BUS_STD = PLBV46
BUS_INTERFACE BUS = LLINK0, BUS_STD = XIL_LL_DMA, BUS_TYPE = INITIATOR
 
 
## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x200, BUS = SPLB, ADDRESS = BASE, PAIR = C_HIGHADDR
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, BUS = SPLB, ADDRESS = HIGH, PAIR = C_BASEADDR
PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)
PARAMETER C_SPLB_SUPPORT_BURSTS = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
PARAMETER C_INCLUDE_DPHASE_TIMER = 0, DT = INTEGER, RANGE = (0, 1)
PARAMETER C_FAMILY = virtex5, DT = STRING
 
## Ports
PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
 
PORT Ll_Clk = "", DIR = I, SIGIS = CLK
PORT Ll_Rst = "", DIR = I, SIGIS = RST
 
# Target
PORT tx_data = LL_Tx_Data, DIR = I, VEC = [31:0], BUS = LLINK0
PORT tx_rem = LL_Tx_Rem, DIR = I, VEC = [3:0], BUS = LLINK0
PORT tx_sof_n = LL_Tx_SOF_n, DIR = I, BUS = LLINK0
PORT tx_eof_n = LL_Tx_EOF_n, DIR = I, BUS = LLINK0
PORT tx_sop_n = LL_Tx_SOP_n, DIR = I, BUS = LLINK0
PORT tx_eop_n = LL_Tx_EOP_n, DIR = I, BUS = LLINK0
PORT tx_src_rdy_n = LL_Tx_SrcRdy_n, DIR = I, BUS = LLINK0
PORT tx_dst_rdy_n = LL_Tx_DstRdy_n, DIR = O, BUS = LLINK0
 
# Initiator
PORT rx_data = LL_Rx_Data, DIR = O, VEC = [31:0], BUS = LLINK0
PORT rx_rem = LL_Rx_Rem, DIR = O, VEC = [3:0], BUS = LLINK0
PORT rx_sof_n = LL_Rx_SOF_n, DIR = O, BUS = LLINK0
PORT rx_eof_n = LL_Rx_EOF_n, DIR = O, BUS = LLINK0
PORT rx_sop_n = LL_Rx_SOP_n, DIR = O, BUS = LLINK0
PORT rx_eop_n = LL_Rx_EOP_n, DIR = O, BUS = LLINK0
PORT rx_src_rdy_n = LL_Rx_SrcRdy_n, DIR = O, BUS = LLINK0
PORT rx_dst_rdy_n = LL_Rx_DstRdy_n, DIR = I, BUS = LLINK0
 
END
 

 

 

 

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Xilinx Employee
Xilinx Employee
7,972 Views
Registered: ‎04-23-2008

Re: Problem running XAPP1129 on a ML405 under EDK9.2

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Try changing this

 OPTION ARCH_SUPPORT_MAP = (OTHERS=DEVELOPMENT)

 

to this

 OPTION ARCH_SUPPORT_MAP = (virtex4=PREFERRED)

 

-Brian

 

View solution in original post

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Xilinx Employee
Xilinx Employee
6,358 Views
Registered: ‎04-23-2008

Re: Problem running XAPP1129 on a ML405 under EDK9.2

Jump to solution

The provided pcore isn't marked as supporting virtex4 (it probably hasn't been tested there).

If you want to try it, you'd edit  the PARAMETER C_FAMILY line ing xapp1129/pcores/xps_ll_example_v1_00_a/data/xps_ll_example_v2_1_0.mpd

I'm sure it's not been tried with EDK 9.2 either...

 

-Brian

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Contributor
Contributor
6,351 Views
Registered: ‎05-27-2009

Re: Problem running XAPP1129 on a ML405 under EDK9.2

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I tried that, i.e. changing the family code to virtex4. Didn't work! That's what makes this so bizarre. However I'll try it again. Perhaps I failed to re import the peripheral the last time.
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Contributor
Contributor
6,340 Views
Registered: ‎05-27-2009

Re: Problem running XAPP1129 on a ML405 under EDK9.2

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Changing the PARAMETER to C_FAMILY = virtex4  makes no difference. Further, if I make a generic peripheral with a virtex4fx20 I'll get a virtex5 as the value of the C_FAMILY PARAMETER.
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Xilinx Employee
Xilinx Employee
7,973 Views
Registered: ‎04-23-2008

Re: Problem running XAPP1129 on a ML405 under EDK9.2

Jump to solution

Try changing this

 OPTION ARCH_SUPPORT_MAP = (OTHERS=DEVELOPMENT)

 

to this

 OPTION ARCH_SUPPORT_MAP = (virtex4=PREFERRED)

 

-Brian

 

View solution in original post

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Contributor
Contributor
6,325 Views
Registered: ‎05-27-2009

Re: Problem running XAPP1129 on a ML405 under EDK9.2

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Nope!

 

Is there any way to make the envoked peripheral .mpd file echo a text string? That way, I can confirm that the file I changed is actually the one I'm compiling.

Is there any way to get more out of the compiler as to what it specifically objects to?

 

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Contributor
Contributor
6,323 Views
Registered: ‎05-27-2009

Re: Problem running XAPP1129 on a ML405 under EDK9.2

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Looks like I repled too quickly. It did work. This time I right clicked on the peripheral from within the system assembly view and found that the .mpd file I had changed within the EDK user repository did no make it's way into the project even though I had rescanned the user repository. Are the peripherals within a project cached somewhere?
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