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giulio.presazzi
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Registered: ‎05-22-2017

Share GPIO ps between Core 0 and Core 1

Dear all,

 

I'm using AMP in Xilinx Zynq-7000 with Linux Embedded on core 0 and bare metal on core 1.

I'm using GPIO both from Core 0 (as gpio-key) and Core 1 (sensor interrupt). I'm able to use that GPIOs when just one core at time is running, but using both cores together  the buttons didn't work anymore.

 

The question is: Is it possibile to share PS GPIO peripheral using some GPIOs in Core0 and some in Core1?

If Yes, how can I do it ?

 

Thanks and regards,

Giulio

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hpoetzl
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Registered: ‎06-24-2013

Hey @giulio.presazzi,

 

Is it possibile to share PS GPIO peripheral using some GPIOs in Core0 and some in Core1?

I don't see a problem with sharing them between the cores.

 

I'm able to use that GPIOs when just one core at time is running, but using both cores together  the buttons didn't work anymore.

This is very likely due to the driver getting confused or simply not notified by changes (interrupts) because the other core already handled them.

 

Note that there is no way to assign a single GPIO pin to a specific core, but for example polling the GPIO status from both sides should not cause any problems.

 

Hope this helps,

Herbert

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hbucher
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Registered: ‎03-22-2016

@giulio.presazzi 32-bit aligned read/writes are atomic and will be resolved by the Zynq. 

You could even access the same GPIO across cores. 

 

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giulio.presazzi
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Registered: ‎05-22-2017

Hi @hpoetzl,

 

I'm able to read successfully the GPIO status from Core0 (linux) in polling mode (gpio-key-polled), and the interrupts work properly in Core1 application (bare metal).

But, as soon as the Core1 is initialized, if the buttons configured in interrupt mode (gpio-key driver), they do not work anymore.

 

Do you have any advice ?

Thanks and regards,

Giulio

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