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Visitor wqvist
Visitor
129 Views
Registered: ‎01-25-2019

U-boot failed to get clock

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I'm using a Zynq 7000 series SoC and am in the midst of upgrading from Petalinux 2015 to 2018.3. Unfortunately I'm stuck on getting the device tree to work.
I've used dtc to convert the created system.dtb to dts, and everything from my dtsi files are incorporated, but it still doesn't work.

What am I doing wrong?

Bootlog:

Xilinx First Stage Boot Loader 
Release 2018.3	Feb 28 2019-12:26:59
Devcfg driver initialized 
Silicon Version 3.1
Watchdog driver initialized 
Boot mode is JTAG
failed to get gem0_emio_clk clock
initcall sequence 0045c0f4 failed at call 00401478 (err=-19)
### ERROR ### Please RESET the board ###

This is my system-user.dtsi:

/include/ "system-conf.dtsi"
#include "video-cap.dtsi"

/ {
	chosen {
		bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p1 rw rootwait cma=128M";
	};

	fixed_emio_clk: fixed_emio_clk {
		compatible = "fixed-clock";
		#clock-cells = <1>;
		clock-frequency = <25000000>;
		clock-output-names = "fixed_emio_clk";
	};
};

&qspi {
      flash0: flash@0 {
           compatible = "spansion,s25fl512s";
     };
};

&clkc {
      clocks = <&fixed_emio_clk 0>;
      clock-names = "gem0_emio_clk";
};

&amba {
	watchdog0: watchdog@f8005000 {
		compatible = "cdns,wdt-r1p2";
		clocks = <&clkc 45>;
		interrupt-parent = <&intc>;
		interrupts = <0 9 1>;
		reg = <0xf8005000 0x1000>;
		reset-on-timeout;
		status = "okay";
		timeout-sec = <10>;
	};

	gem0: ethernet@e000b000 {
		compatible = "cdns,gem";
		reg = <0xe000b000 0x1000>;
		status = "okay";
		interrupts = <0x0 0x16 0x4>;
		clocks = <0x1 0x1e 0x1 0x1e 0x1 0xd>;
		clock-names = "pclk", "hclk", "tx_clk";
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		enet-reset = <0x4 0x2f 0x0>;
		phy-mode = "gmii-id";
		xlnx,ptp-enet-clock = <0x69f6bcb>;
		local-mac-address = [00 0a 35 00 1e 53];
		phy-handle = <0x5>;

		ps7_ethernet_0_mdio: mdio {
			#address-cells = <0x1>;
			#size-cells = <0x0>;

			phy0: phy@0 {
				compatible = "microchip,lan8710a";
				device_type = "ethernet-phy";
				reg = <0x0>;
				linux,phandle = <0x5>;
				phandle = <0x5>;
			};
		};
	};
};
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1 Solution

Accepted Solutions
Scholar xilinxacct
Scholar
117 Views
Registered: ‎10-23-2018

Re: U-boot failed to get clock

Jump to solution

@wqvist 

Does this apply to your case?

https://forums.xilinx.com/t5/Embedded-Processor-System-Design/uboot-failed-MMC-sdhci-set-clock-Internal-clock-never/m-p/789185#M24076

Hope that helps.

If so, please mark as solution accepted. Kudos also welcomed. :-)

1 Reply
Scholar xilinxacct
Scholar
118 Views
Registered: ‎10-23-2018

Re: U-boot failed to get clock

Jump to solution

@wqvist 

Does this apply to your case?

https://forums.xilinx.com/t5/Embedded-Processor-System-Design/uboot-failed-MMC-sdhci-set-clock-Internal-clock-never/m-p/789185#M24076

Hope that helps.

If so, please mark as solution accepted. Kudos also welcomed. :-)