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mrberman87
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Registered: ‎11-15-2017

UltraZed-EG Displayport and X11 No Screen Problem

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I am running the UltraZed-EG with the PCIe-CC.  I am building with Yocto, but against all of the petalinux repos at branch 2019.2, and I am also using my own xsa file from my own project.  I am trying to get the Displayport up and running, but I am having what appears to be driver issues.  When I try to start X, I get an error that there are no Screens and X does not start.  In the Xorg.0.log, it appears that /dev/dri/card0 is what is chosen, but the displayport is for some reason mapped to /dev/dri/card2.  This is shown in the terminal.txt; I also included a modetest -M xlnx output in the terminal.txt.  I have also attached a copy of my device tree, xorg.conf, and a dmesg printout for reference.  I have also included the full kernel configuration.

I don't know where to go from here, any help or troubleshooting advice would be appreciated.

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sandeepg
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Registered: ‎04-24-2017

Hi @mrberman87 ,

I was able to get this working, issue is in ultrazed pciecc board files in vivado. Below is the steps you need to follow.

  1. Clone the Ultrazed PCIeCC board files https://github.com/Avnet/bdf/tree/master/ultrazed_3eg_pciecc make sure you use 1.2 version
  2. Launch vivado tools and from "tcl console" run below command.
    set_param board.repoPaths <path-to>/avnet/bdf/ultrazed_3eg_pciecc
    
  3. Source attached tcl file.
    source ./uz3eg_pciecc.tcl
  4. Build vivado design and export the xsa.
  5. Use this exported XSA in Yocto project to build the images. Make sure you make add below device-tree nodes for PCIeCC board.
    &gem3 {
    	status = "okay";
    	local-mac-address = [00 0a 35 00 02 90];
    	phy-mode = "rgmii-id";
    	phy-handle = <&phy0>;
    	phy0: phy@9 {
    		reg = <0x9>;
    		ti,rx-internal-delay = <0x5>;
    		ti,tx-internal-delay = <0x5>;
    		ti,fifo-depth = <0x1>;
    	};
    };
    
    &i2c1 {
    	status = "okay";
    	clock-frequency = <400000>;
    
    	i2c-mux@70 { /* U7 on UZ3EG SOM */
    		compatible = "nxp,pca9542";
    		#address-cells = <1>;
    		#size-cells = <0>;
    		reg = <0x70>;
    		i2c@0 { /* i2c mw 70 0 1 */
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <0>;
    			/* IIC_EEPROM */
    			eeprom: eeprom@51 { /* U5 on UZ3EG IOCC and U7 on the UZ7EV EVCC*/
    				compatible = "atmel,24c08";
    				reg = <0x51>;
    			};
    		};
    	};
    };
    
    &qspi {
    	#address-cells = <1>;
    	#size-cells = <0>;
    	status = "okay";
    	is-dual = <1>; /* Set for dual-parallel QSPI config */
    	num-cs = <2>;
    	xlnx,fb-clk = <0x1>;
    	flash0: flash@0 {
            /* The Flash described below doesn't match our board ("micron,n25qu256a"), but is needed */
            /* so the Flash MTD partitions are correctly identified in /proc/mtd */
    		compatible = "micron,m25p80"; /* 32MB */
    		#address-cells = <1>;
    		#size-cells = <1>;
    		reg = <0x0>;
    		spi-tx-bus-width = <1>;
    		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
    		spi-max-frequency = <108000000>; /* Set to 108000000 Based on DC1 spec */
    	};
    };
    
    /* SD0 eMMC, 8-bit wide data bus */
    &sdhci0 {
    	status = "okay";
    	bus-width = <8>;
    	max-frequency = <50000000>;
    };
    
    /* SD1 with level shifter */
    &sdhci1 {
    	status = "okay";
    	max-frequency = <50000000>;
    	no-1-8-v;	/* for 1.0 silicon */
    };
    
    /* ULPI SMSC USB3320 */
    &usb0 {
    	status = "okay";
    };
    
    &dwc3_0 {
    	status = "okay";
    	dr_mode = "host";
    	phy-names = "usb3-phy";
    };
  6. Enable X11 and other packages.
    IMAGE_INSTALL_append = "\
    		libmali-xlnx \
    		packagegroup-petalinux-display-debug \
    		packagegroup-petalinux-x11 \
    		tricube \
    		"

 

Thanks,
Sandeep
PetaLinux Yocto | Embedded SW Support

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florentw
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Registered: ‎11-09-2015

Hi @mrberman87 

The modetest output is not returning anything so I am not sure the display is correcly detected.

I assume the ultrazed board as a pre-built image you can test with first? This could help checking that this is not an hardware issue?

If the pre-built image is not working as well you need to check your HW:

  • What is the model of your monitor? Is it a DP1.1/1.2 or 1.4 compliant monitor
  • Is it connected using a Displayport cable? i.e. no Displayport to HDMI adapters. Note that as per AR#71774, Xilinx does not support the use of adapters. Passive DP to HDMI adapters will not work for sure. Active DP to HDMI adapters could work but this is up to the user to do their own characterization

Florent
Product Application Engineer - Xilinx Technical Support EMEA
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mrberman87
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Registered: ‎11-15-2017

I have an old pre-built image that works with this hardware set.  The monitor is a Dell E2216H, I cannot find the DisplayPort version it is built to.  I am connecting with DisplayPort directly from the SDK board to the monitor, there is nothing in between.

I cannot get X to start at all, not even to run x11vnc or anything else in the background.

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florentw
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Hi @mrberman87 

If the monitor is able to work with the pre-built image, then that rules out the issue with the hardware.

So it has to be coming from the vivado design or the linux application.

Would you be able to provide the output of the modetest command from the pre-built image?

A suggestion I have is to compare the ZynqMPSoC configuration with the base project from AVNET.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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mrberman87
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I am trying to compare against the Avnet project, but there are a lot of differences.  The linux branches are different and complete different versions, and the display drivers and clocking configuration has completely changed.  The Avnet example was written for 2017.2, and I am trying to build with 2019.2.

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florentw
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Registered: ‎11-09-2015

HI @mrberman87 

If you look on the following page, you will have the BSP for the board build for 2019.1 (UltraZed-EG PCIe Carrier Card - PetaLinux 2019.1 Enhanced BSP)

http://www.ultrazed.org/support/design/17956/141

The BSP is a petalinux project packaged. It might contain the vivado design as well. This might give you a closer reference


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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mrberman87
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I have compared what I have against several of the reference designs.

Looking at the Wiki page (https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842105/ZynqMP+DisplayPort+Linux+driver) for this, if I enable the pre-2018.1 device drivers, I am able to get the X sub-system up and running, and I am able to use x11vnc to remotely connect to the device, although I still have no outputs from the physical Display port.  If I disable the old drivers in the kernel and only leave the newer drivers, I have errors when starting the X sub-system.  I am not modifying the device tree for any of the Display port nodes in the device tree, I am letting what is defined in the recipes do whatever they are normally doing for these nodes.  I don't know where I am going wrong with this.

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florentw
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HI @mrberman87 

Did you first ensure that the configuration of the Displayport was the same in the ZynqMP configuration wizard in Vivado between your design and the reference designs? (check the lane assignment and the source for the PLL (to be VPLL))


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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mrberman87
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Yes, I have verified that I am using the correct hardware setup from Vivado.  I am using the single lane, on GTR 3, which lines up with the Ultrazed PCIe-CC pcb.  I am configuring the external clock to feed in the 27 MHz reference for the GTR channel.  I have the Displayport subsystem using the VPLL, and that is the only block using that PLL.

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florentw
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Hi @mrberman87 

Ok then the second step to debug would be to use the BSP provided by AVNET for the board to create your base petalinux project and import your hdf/xsa file. The BSP should have all the dependencies for the DP enabled.

petalinux-create -t project -s <path to bsp> -n <project name>
cd <project name>
petalinux-config --get-hw-description <path to xsa/hdf>

If this doesn't work it means that there is still something wrong in the ZynqMP configuration we would need to narrow down


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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mrberman87
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Florent,

I have looked at the configurations, and I have things working a little bit more than before.  I am able to see the display configuration in the modetest command, and I am seeing in the /sys directories that the DisplayPort is connected.  I am still having issues with clocking however.  I have added a few debug print statements, but this is showing that I cannot correctly set the VPLL for the pixel clock.  The DisplayPort is the only peripheral that the VPLL is connected to in the Vivado clock configuration.  To show what the test prints are outputting, and where, I have attached the patch that inserts them.  Where could I look further to get this working?

 

 

root@zynqmp:~# modetest -D fd4a0000.zynqmp-display -s 39@37:1280x720-60@AR24 &
root@zynqmp:~# setting mode 1280x720-60Hz@AR24 on connectors 39, crtc 37
[  309.128939] zynqmp-display fd4a0000.zynqmp-display: TEST -- zynqmp_dp_mode_configure() 617 --> 540000 1 20 24 0 74250
[  309.143356] zynqmp-display fd4a0000.zynqmp-display: TEST -- zynqmp_dp_mode_configure() 632 --> 2 20
[  309.152515] zynqmp-display fd4a0000.zynqmp-display: TEST -- zynqmp_dp_mode_configure() 640 --> 1 540000 180000
[  309.163259] TEST -- zynqmp_pll_set_rate() 96 'vpll_int' 1 1 0
[  309.169019] ------------[ cut here ]------------
[  309.173640] More than allowed devices are using the vpll_int, which is forbidden
[  309.181069] WARNING: CPU: 3 PID: 2923 at drivers/clk/zynqmp/pll.c:195 zynqmp_pll_set_rate+0x274/0x2a8
[  309.190276] Modules linked in: mali(O)
[  309.194021] CPU: 3 PID: 2923 Comm: modetest Tainted: G        W  O      4.19.0-xilinx-v2019.1 #1
[  309.202792] Hardware name: Avnet UltraZed-3EG (DT)
[  309.209912] pstate: 40000005 (nZcv daif -PAN -UAO)
[  309.214694] pc : zynqmp_pll_set_rate+0x274/0x2a8
[  309.219303] lr : zynqmp_pll_set_rate+0x274/0x2a8
[  309.223911] sp : ffffff800dafb840
[  309.227209] x29: ffffff800dafb840 x28: 0000000000000000
[  309.232513] x27: ffffff8008a7fcd8 x26: 00000000ffffffa9
[  309.237816] x25: ffffff8008b15f40 x24: 0000000000000060
[  309.243120] x23: ffffffc06ca1a200 x22: 0000000001fca055
[  309.248423] x21: 0000000000000031 x20: ffffff80091b8648
[  309.253727] x19: 0000000000310147 x18: 0000000000000010
[  309.259030] x17: 0000000000000000 x16: 0000000000000000
[  309.264334] x15: ffffffffffffffff x14: ffffff80091b8648
[  309.269637] x13: ffffff80892b759f x12: ffffff80092b75a7
[  309.274941] x11: ffffff80091c9000 x10: ffffff800dafb540
[  309.280244] x9 : 00000000ffffffd0 x8 : 206863696877202c
[  309.285548] x7 : 746e695f6c6c7076 x6 : ffffffc07feb86a0
[  309.290851] x5 : ffffffc07feb86a0 x4 : 0000000000000000
[  309.296155] x3 : 0000000000000001 x2 : 0000000000000000
[  309.301458] x1 : 275906e2e7603d00 x0 : 0000000000000000
[  309.306762] Call trace:
[  309.309195]  zynqmp_pll_set_rate+0x274/0x2a8
[  309.313458]  clk_change_rate+0x164/0x258
[  309.317372]  clk_core_set_rate_nolock+0x100/0x1b0
[  309.322067]  clk_set_rate+0x34/0xa0
[  309.325550]  zynqmp_disp_crtc_atomic_enable+0x58/0x2d8
[  309.330679]  drm_atomic_helper_commit_modeset_enables+0x1d4/0x210
[  309.336762]  drm_atomic_helper_commit_tail+0x3c/0x78
[  309.341718]  commit_tail+0x74/0x78
[  309.345112]  drm_atomic_helper_commit+0xc8/0x140
[  309.349724]  drm_atomic_commit+0x48/0x58
[  309.353636]  drm_atomic_helper_set_config+0xa0/0xb0
[  309.358507]  drm_mode_setcrtc+0x144/0x5d8
[  309.362508]  drm_ioctl_kernel+0xb4/0x100
[  309.366422]  drm_ioctl+0x234/0x3d0
[  309.369818]  do_vfs_ioctl+0xb8/0x890
[  309.373384]  ksys_ioctl+0x78/0xa8
[  309.376691]  __arm64_sys_ioctl+0x1c/0x28
[  309.380607]  el0_svc_common+0x84/0xd8
[  309.384260]  el0_svc_handler+0x2c/0x80
[  309.388002]  el0_svc+0x8/0xc
[  309.390873] ---[ end trace 31a3dae4fcba6ecf ]---
[  309.395492] zynqmp_pll_set_rate() set divider failed for vpll_int, ret = -87
[  309.402806] zynqmp-display fd4a0000.zynqmp-display: request pixel rate: 74250 actual rate: 300016629
[  309.506467] zynqmp-display fd4a0000.zynqmp-display: TEST -- zynqmp_dp_mode_configure() 617 --> 540000 1 20 24 20 74250
[  309.517162] zynqmp-display fd4a0000.zynqmp-display: TEST -- zynqmp_dp_mode_configure() 632 --> 1 10
[  309.526214] zynqmp-display fd4a0000.zynqmp-display: TEST -- zynqmp_dp_mode_configure() 640 --> 1 270000 90000
[  309.548597] zynqmp-display fd4a0000.zynqmp-display: TEST -- zynqmp_dp_mode_configure() 617 --> 540000 1 20 24 10 74250
[  309.559288] zynqmp-display fd4a0000.zynqmp-display: TEST -- zynqmp_dp_mode_configure() 632 --> 0 6
[  309.568251] zynqmp-display fd4a0000.zynqmp-display: TEST -- zynqmp_dp_mode_configure() 640 --> 1 162000 54000
[  309.578164] zynqmp-display fd4a0000.zynqmp-display: failed to configure link values
[  309.585826] zynqmp-display fd4a0000.zynqmp-display: failed to train the DP link

[1]+  Stopped(SIGTTIN)        modetest -M xilinx_drm -D fd4a0000.zynqmp-display -s 39@37:1280x720-60@AR24

 

 

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florentw
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Registered: ‎11-09-2015

Hi @mrberman87 

Could you do a write_bd.tcl and share the file? I want to look at the ZynqMP configuration because your log still mention the following:

More than allowed devices are using the vpll_int, which is forbidden

Florent
Product Application Engineer - Xilinx Technical Support EMEA
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mrberman87
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Please find the attached write_bd_tcl output.

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florentw
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HI @mrberman87 

Thank you.

I am comparing the clock configuration with what is used in the ZCU102 which is my reference. Could you try to change the PLL for the DP_STC to RPLL:

Dp.JPG


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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mrberman87
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I made the suggested change, but this has made no effect on the issue.  I am still getting the error message about multiple sources trying to control vpll clock.

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sandeepg
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Registered: ‎04-24-2017

Hi @mrberman87 ,

I was able to get this working, issue is in ultrazed pciecc board files in vivado. Below is the steps you need to follow.

  1. Clone the Ultrazed PCIeCC board files https://github.com/Avnet/bdf/tree/master/ultrazed_3eg_pciecc make sure you use 1.2 version
  2. Launch vivado tools and from "tcl console" run below command.
    set_param board.repoPaths <path-to>/avnet/bdf/ultrazed_3eg_pciecc
    
  3. Source attached tcl file.
    source ./uz3eg_pciecc.tcl
  4. Build vivado design and export the xsa.
  5. Use this exported XSA in Yocto project to build the images. Make sure you make add below device-tree nodes for PCIeCC board.
    &gem3 {
    	status = "okay";
    	local-mac-address = [00 0a 35 00 02 90];
    	phy-mode = "rgmii-id";
    	phy-handle = <&phy0>;
    	phy0: phy@9 {
    		reg = <0x9>;
    		ti,rx-internal-delay = <0x5>;
    		ti,tx-internal-delay = <0x5>;
    		ti,fifo-depth = <0x1>;
    	};
    };
    
    &i2c1 {
    	status = "okay";
    	clock-frequency = <400000>;
    
    	i2c-mux@70 { /* U7 on UZ3EG SOM */
    		compatible = "nxp,pca9542";
    		#address-cells = <1>;
    		#size-cells = <0>;
    		reg = <0x70>;
    		i2c@0 { /* i2c mw 70 0 1 */
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <0>;
    			/* IIC_EEPROM */
    			eeprom: eeprom@51 { /* U5 on UZ3EG IOCC and U7 on the UZ7EV EVCC*/
    				compatible = "atmel,24c08";
    				reg = <0x51>;
    			};
    		};
    	};
    };
    
    &qspi {
    	#address-cells = <1>;
    	#size-cells = <0>;
    	status = "okay";
    	is-dual = <1>; /* Set for dual-parallel QSPI config */
    	num-cs = <2>;
    	xlnx,fb-clk = <0x1>;
    	flash0: flash@0 {
            /* The Flash described below doesn't match our board ("micron,n25qu256a"), but is needed */
            /* so the Flash MTD partitions are correctly identified in /proc/mtd */
    		compatible = "micron,m25p80"; /* 32MB */
    		#address-cells = <1>;
    		#size-cells = <1>;
    		reg = <0x0>;
    		spi-tx-bus-width = <1>;
    		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
    		spi-max-frequency = <108000000>; /* Set to 108000000 Based on DC1 spec */
    	};
    };
    
    /* SD0 eMMC, 8-bit wide data bus */
    &sdhci0 {
    	status = "okay";
    	bus-width = <8>;
    	max-frequency = <50000000>;
    };
    
    /* SD1 with level shifter */
    &sdhci1 {
    	status = "okay";
    	max-frequency = <50000000>;
    	no-1-8-v;	/* for 1.0 silicon */
    };
    
    /* ULPI SMSC USB3320 */
    &usb0 {
    	status = "okay";
    };
    
    &dwc3_0 {
    	status = "okay";
    	dr_mode = "host";
    	phy-names = "usb3-phy";
    };
  6. Enable X11 and other packages.
    IMAGE_INSTALL_append = "\
    		libmali-xlnx \
    		packagegroup-petalinux-display-debug \
    		packagegroup-petalinux-x11 \
    		tricube \
    		"

 

Thanks,
Sandeep
PetaLinux Yocto | Embedded SW Support

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mrberman87
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Thanks for the help Sandeepg!  This worked for me as well, and I was able to use this build's PS configuration to modify the configuration I had.  This has allowed my custom Yocto build to work.