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flutnic
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Registered: ‎05-26-2020

Ultrascale+ "FPGA fail to get the done status"

Hi all!!

I have the MYD-CZU3EG-4E4D-1200-C board from MYIR (http://www.myirtech.com/list.asp?id=613). I connect to the board via the USB to UART port and when I try to configure the PL part I always get this error: "FPGA fail to get the done status"

 

The commands that I execute as root are:

> cp design_1_wrapper.bin /lib/firmware

> echo design_1_wrapper.bin > /sys/class/fpga_manager/fpga0/firmware

 

I found that there is a "solution" in here (https://www.xilinx.com/support/answers/70504.html) but I don't understand what should I do to solve this problem. Does anybody knows a solution for this problem or can tell me what to do?

Thanks in advance

 

 

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flutnic
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Registered: ‎05-26-2020

Well, after reading carefully this: https://www.xilinx.com/support/answers/70504.html ... does it mean that I have to edit the xilfpga.c files that are installed with Vivado ? And then what? I run a new synth and implementation ?

 

Thanks in advance

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