UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor maoleilei
Visitor
274 Views
Registered: ‎05-20-2018

VDMA CLOCK

The VDMA IP core I added has errors in the device tree.It can‘t get misc_clk_0 ,But I put all the clocks on pl_clk_0.

 

clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_s2mm_aclk";

clocks = <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>;

 

misc_clk_0: misc_clk_0 {
  };

 

0 Kudos