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Registered: ‎05-20-2018

VDMA CLOCK

The VDMA IP core I added has errors in the device tree.It can‘t get misc_clk_0 ,But I put all the clocks on pl_clk_0.

 

clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_s2mm_aclk";

clocks = <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>;

 

misc_clk_0: misc_clk_0 {
  };

 

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