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Visitor
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7,972 Views
Registered: ‎07-03-2009

Virtex4 - PPC405 Boot Problem

Hi All,

  I'm trying to bring up the linux in a Custom board which is very close to ML405 except that our board has DDR2 Memory.

 

Please find my MHS below

 


# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 10.1.03 Build EDK_K_SP3.6
# Thu Nov 20 13:47:20 2008
# Target Board:  Custom
# Family:    virtex4
# Device:    xc4vfx100
# Package:   ff1517
# Speed Grade:  -11
# Processor: ppc405_0
# Processor clock frequency: 125.00 MHz
# Bus clock frequency: 62.50 MHz
# On Chip Memory :  64 KB
# Total Off Chip Memory : 256 MB
# - DDR2_SDRAM_W1D32M72R8A_5A = 256 MB
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I
 PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O
 PORT fpga_0_LEDS_GPIO_d_out_pin = fpga_0_LEDS_GPIO_d_out, DIR = O, VEC = [0:3]
 PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_ODT, DIR = O
 PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Addr_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Addr, DIR = O, VEC = [12:0]
 PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_BankAddr_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_BankAddr, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CAS_n_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CAS_n, DIR = O
 PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CE_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CE, DIR = O
 PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CS_n_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CS_n, DIR = O
 PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_RAS_n_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_RAS_n, DIR = O
 PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_WE_n_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_WE_n, DIR = O
 PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DM_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DM, DIR = O, VEC = [7:0]
 PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS, DIR = IO, VEC = [7:0]
 PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS_n = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS_n, DIR = IO, VEC = [7:0]
 PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQ = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQ, DIR = IO, VEC = [63:0]
 PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk_n_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk_n, DIR = O, VEC = [1:0]
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 125000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST


BEGIN ppc405_virtex4
 PARAMETER INSTANCE = ppc405_0
 PARAMETER HW_VER = 2.01.a
 PARAMETER C_FASTEST_PLB_CLOCK = DPLB1
 PARAMETER C_IDCR_BASEADDR = 0b0100000000
 PARAMETER C_IDCR_HIGHADDR = 0b0111111111
 BUS_INTERFACE IPLB0 = plb
 BUS_INTERFACE DPLB0 = plb
 BUS_INTERFACE IPLB1 = ppc405_0_iplb1
 BUS_INTERFACE DPLB1 = ppc405_0_dplb1
 BUS_INTERFACE JTAGPPC = jtagppc_cntlr_0_0
 BUS_INTERFACE RESETPPC = ppc_reset_bus
 PORT CPMC405CLOCK = proc_clk_s
 PORT EICC405EXTINPUTIRQ = xps_intc_0_Irq
END

BEGIN plb_v46
 PARAMETER INSTANCE = plb
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
 PARAMETER HW_VER = 1.03.a
 PORT PLB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
 PORT Bus_Error_Det = plb_Bus_Error_Det
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = xps_bram_if_cntlr_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SPLB_NATIVE_DWIDTH = 64
 PARAMETER C_BASEADDR = 0xffff0000
 PARAMETER C_HIGHADDR = 0xffffffff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN bram_block
 PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN xps_gpio
 PARAMETER INSTANCE = LEDS
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_BASEADDR = 0x81400000
 PARAMETER C_HIGHADDR = 0x8140ffff
 BUS_INTERFACE SPLB = plb
 PORT GPIO_d_out = fpga_0_LEDS_GPIO_d_out
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SPLB_CLK_FREQ_HZ = 62500000
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = plb
 PORT RX = fpga_0_RS232_RX
 PORT TX = fpga_0_RS232_TX
 PORT Interrupt = RS232_Interrupt
END

BEGIN mpmc
 PARAMETER INSTANCE = DDR2_SDRAM_W1D32M72R8A_5A
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_NUM_PORTS = 2
 PARAMETER C_MEM_PARTNO = CUSTOM
 PARAMETER C_PIM1_BASETYPE = 2
 PARAMETER C_MPMC_CLK0_PERIOD_PS = 8000
 PARAMETER C_MEM_CE_WIDTH = 1
 PARAMETER C_MEM_ODT_WIDTH = 1
 PARAMETER C_MEM_CLK_WIDTH = 2
 PARAMETER C_MEM_CS_N_WIDTH = 1
 PARAMETER C_MEM_NUM_RANKS = 1
 PARAMETER C_MEM_REG_DIMM = 0
 PARAMETER C_MEM_PART_DATA_DEPTH = 64
 PARAMETER C_MEM_PART_DATA_WIDTH = 16
 PARAMETER C_MEM_PART_NUM_COL_BITS = 10
 PARAMETER C_MEM_PART_CAS_A_FMAX = 200
 PARAMETER C_MEM_PART_CAS_A = 5
 PARAMETER C_MEM_PART_TRAS = 45000
 PARAMETER C_MEM_PART_TRASMAX = 70000000
 PARAMETER C_MEM_PART_TRC = 60000
 PARAMETER C_MEM_PART_CAS_B_FMAX = 200
 PARAMETER C_MEM_PART_CAS_B = 4
 PARAMETER C_MEM_PART_TWTR = 7500
 PARAMETER C_MEM_PART_TWR = 15000
 PARAMETER C_MEM_PART_TCCD = 2
 PARAMETER C_MEM_PART_TRRD = 10000
 PARAMETER C_MEM_PART_TRCD = 15000
 PARAMETER C_MEM_PART_TREFI = 7800000
 PARAMETER C_MEM_PART_TRFC = 105000
 PARAMETER C_MEM_PART_TRP = 15000
 PARAMETER C_MPMC_BASEADDR = 0x00000000
 PARAMETER C_MPMC_HIGHADDR = 0x0fffffff
 BUS_INTERFACE SPLB0 = ppc405_0_iplb1
 BUS_INTERFACE SPLB1 = ppc405_0_dplb1
 PORT DDR2_ODT = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_ODT
 PORT DDR2_Addr = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Addr
 PORT DDR2_BankAddr = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_BankAddr
 PORT DDR2_CAS_n = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CAS_n
 PORT DDR2_CE = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CE
 PORT DDR2_CS_n = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CS_n
 PORT DDR2_RAS_n = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_RAS_n
 PORT DDR2_WE_n = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_WE_n
 PORT DDR2_DM = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DM
 PORT DDR2_DQS = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS
 PORT DDR2_DQS_n = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS_n
 PORT DDR2_DQ = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQ
 PORT DDR2_Clk = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk
 PORT DDR2_Clk_n = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk_n
 PORT MPMC_Clk0 = proc_clk_s
 PORT MPMC_Clk90 = DDR2_SDRAM_W1D32M72R8A_5A_mpmc_clk_90_s
 PORT MPMC_Clk_200MHz = clk_200mhz_s
 PORT MPMC_Rst = sys_periph_reset
END

BEGIN plb_v46
 PARAMETER INSTANCE = ppc405_0_iplb1
 PARAMETER HW_VER = 1.03.a
 PORT PLB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
 PORT Bus_Error_Det = ppc405_0_iplb1_Bus_Error_Det
END

BEGIN plb_v46
 PARAMETER INSTANCE = ppc405_0_dplb1
 PARAMETER HW_VER = 1.03.a
 PORT PLB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
 PORT Bus_Error_Det = ppc405_0_dplb1_Bus_Error_Det
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 2.01.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_CLKIN_FREQ = 125000000
 PARAMETER C_CLKOUT0_FREQ = 62500000
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = DCM0
 PARAMETER C_CLKOUT1_FREQ = 125000000
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = DCM0
 PARAMETER C_CLKOUT2_FREQ = 125000000
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_CLKOUT2_PHASE = 90
 PARAMETER C_CLKOUT2_GROUP = DCM0
 PARAMETER C_CLKOUT3_FREQ = 200000000
 PARAMETER C_CLKOUT3_BUF = TRUE
 PARAMETER C_CLKOUT3_PHASE = 0
 PARAMETER C_CLKOUT3_GROUP = NONE
 PORT CLKOUT0 = sys_clk_s
 PORT CLKOUT1 = proc_clk_s
 PORT CLKOUT2 = DDR2_SDRAM_W1D32M72R8A_5A_mpmc_clk_90_s
 PORT CLKOUT3 = clk_200mhz_s
 PORT CLKIN = dcm_clk_s
 PORT LOCKED = Dcm_all_locked
 PORT RST = net_gnd
END

BEGIN jtagppc_cntlr
 PARAMETER INSTANCE = jtagppc_cntlr_0
 PARAMETER HW_VER = 2.01.c
 BUS_INTERFACE JTAGPPC0 = jtagppc_cntlr_0_0
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 BUS_INTERFACE RESETPPC0 = ppc_reset_bus
 PORT Slowest_sync_clk = sys_clk_s
 PORT Dcm_locked = Dcm_all_locked
 PORT Ext_Reset_In = sys_rst_s
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END

BEGIN xps_intc
 PARAMETER INSTANCE = xps_intc_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x81800000
 PARAMETER C_HIGHADDR = 0x8180ffff
 BUS_INTERFACE SPLB = plb
 PORT Intr = ppc405_0_iplb1_Bus_Error_Det&ppc405_0_dplb1_Bus_Error_Det&plb_Bus_Error_Det&RS232_Interrupt
 PORT Irq = xps_intc_0_Irq
END


I could run TestAPP_Memory sucessfully. This confirms me that my hardware is working good.

 

In order to run a linux on the board, i have followed exactly mentioned on xilinx.wikidot.com

 

I generated .dts file using device-tree-generator. Please find below the generated file for your reference

 

/*
 * Device Tree Generator version: 1.2
 *
 * (C) Copyright 2007-2008 Xilinx, Inc.
 * (C) Copyright 2007-2008 Michal Simek
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * CAUTION: This file is automatically generated by libgen.
 * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
 *
 * XPS project directory: Linux
 */

/dts-v1/;
/ {
    #address-cells = <1>;
    #size-cells = <1>;
    compatible = "xlnx,virtex405", "xlnx,virtex";
    model = "testing";
    DDR2_SDRAM_W1D32M72R8A_5A: memory@0 {
        device_type = "memory";
        reg = < 0x0 0x10000000 >;
    } ;
    alias {
        serial0 = &RS232;
    } ;
    chosen {
        bootargs = "console=ttyUL0 root=/dev/ram";
        linux,stdout-path = "/plb@0/serial@84000000";
    } ;
    cpus {
        #address-cells = <1>;
        #cpus = <0x1>;
        #size-cells = <0>;
        ppc405_0: cpu@0 {
            clock-frequency = <125000000>;
            compatible = "PowerPC,405", "ibm,ppc405";
            d-cache-line-size = <0x20>;
            d-cache-size = <0x4000>;
            dcr-access-method = "native";
            dcr-controller ;
            device_type = "cpu";
            i-cache-line-size = <0x20>;
            i-cache-size = <0x4000>;
            model = "PowerPC,405";
            reg = <0>;
            timebase-frequency = <125000000>;
            xlnx,apu-control = <0xde00>;
            xlnx,apu-udi-1 = <0xa18983>;
            xlnx,apu-udi-2 = <0xa38983>;
            xlnx,apu-udi-3 = <0xa589c3>;
            xlnx,apu-udi-4 = <0xa789c3>;
            xlnx,apu-udi-5 = <0xa98c03>;
            xlnx,apu-udi-6 = <0xab8c03>;
            xlnx,apu-udi-7 = <0xad8c43>;
            xlnx,apu-udi-8 = <0xaf8c43>;
            xlnx,deterministic-mult = <0x0>;
            xlnx,disable-operand-forwarding = <0x1>;
            xlnx,fastest-plb-clock = "DPLB0";
            xlnx,generate-plb-timespecs = <0x1>;
            xlnx,mmu-enable = <0x1>;
            xlnx,pvr-high = <0x0>;
            xlnx,pvr-low = <0x0>;
        } ;
    } ;
    plb: plb@0 {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
        ranges ;
        LEDS: gpio@81400000 {
            compatible = "xlnx,xps-gpio-1.00.a";
            reg = < 0x81400000 0x10000 >;
            xlnx,all-inputs = <0x0>;
            xlnx,all-inputs-2 = <0x0>;
            xlnx,dout-default = <0x0>;
            xlnx,dout-default-2 = <0x0>;
            xlnx,family = "virtex4";
            xlnx,gpio-width = <0x4>;
            xlnx,interrupt-present = <0x0>;
            xlnx,is-bidir = <0x0>;
            xlnx,is-bidir-2 = <0x1>;
            xlnx,is-dual = <0x0>;
            xlnx,tri-default = <0xffffffff>;
            xlnx,tri-default-2 = <0xffffffff>;
        } ;
        RS232: serial@84000000 {
            clock-frequency = <62500000>;
            compatible = "xlnx,xps-uartlite-1.00.a";
            current-speed = <9600>;
            device_type = "serial";
            interrupt-parent = <&xps_intc_0>;
            interrupts = < 0 0 >;
            port-number = <0>;
            reg = < 0x84000000 0x10000 >;
            xlnx,baudrate = <0x2580>;
            xlnx,data-bits = <0x8>;
            xlnx,family = "virtex4";
            xlnx,odd-parity = <0x1>;
            xlnx,use-parity = <0x1>;
        } ;
        xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
            compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
            reg = < 0xffff0000 0x10000 >;
            xlnx,family = "virtex4";
        } ;
        xps_intc_0: interrupt-controller@81800000 {
            #interrupt-cells = <0x2>;
            compatible = "xlnx,xps-intc-1.00.a";
            interrupt-controller ;
            reg = < 0x81800000 0x10000 >;
            xlnx,num-intr-inputs = <0x4>;
        } ;
    } ;
    ppc405_0_dplb1: plb@1 {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
        ranges ;
        mpmc@0 {
            #address-cells = <1>;
            #size-cells = <1>;
            compatible = "xlnx,mpmc-4.03.a";
        } ;
    } ;
}  ;
 

 

I have downloaded ELDK 4.2 version and installed it on Red Hat 9 Linux machine. I have created the cross compiler for ppc_4xx- and binary are placed in my $path.

 

I have downloaded linux-2.6-xlnx.git  snapshot from http://git.xilinx.com.

 

To begin with, i have created my kernel configuration file by running the following command 

 

make ARCH=powerpc 40x/virtex4_defconfig

 

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And i edited it to enable Xilinx UART and made it as console by running "make menuconfig"

 

I have downloaded 8MB ramdisk image from this forum and placed in arch/powerpc/boot dir

 

I have configured my block ram as 8192 in my kernel.

 

Pleasef find my .config file attached

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-- Continuation of Previous Post 

 

 

 I have created the .elf file by the following command

 

make ARCH=powerpc simpleImage.initrd.virtex405-mine

 

 Now, when i download it my board, Kernel is not executing and it got struct at bootloader phase.

 

 

 

zImage starting: loaded at 0x00400000 (sp: 0x00859eb0)
Allocating 0x3686fc bytes for kernel ...
gunzipping (0x00000000 <- 0x0040c000:0x005958d0)...

 

 

 I was trying to debug it by stop command in XMD and tried reading the program counter. Please find the register values below

 

 

XMD% rrd
    r0: 0085a71c      r8: ffffffff     r16: ffffffff     r24: 0085a95c
    r1: 00859de0      r9: 00000056     r17: 000001ff     r25: 0085b32c
    r2: ffff9390     r10: 0033ffe5     r18: 0000003f     r26: 00000000
    r3: 000000e3     r11: 00000000     r19: 00008000     r27: 0085a400
    r4: 0085c95b     r12: 0033ffe5     r20: 00008000     r28: 0085a430
    r5: 00000001     r13: ffff94c0     r21: 0085c95c     r29: 000d1856
    r6: fffffeff     r14: 0018966b     r22: 00345e06     r30: 0018966b
    r7: 0086148a     r15: 00008000     r23: 005958ca     r31: 0040996c
    pc: 89400700     msr: 00000000
XMD%

 

Is my steps are right or did my i miss anything ?

 

 Can someone guide me with debug suggestion ??

 

 

Finally, I apologize for writing such a long post :-)

 

 

 

Thanks

Rajesh RV

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Xilinx Employee
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Registered: ‎09-10-2008

Hi,

 

I don't see anything obviously wrong with a quick look.  The output from the bootstrap loader without any kernel output are usually a sign of a bad device tree or a the wrong console setup.  Your console setup looks fine as you have the kernel config setup for uart lite and the kernel command line in the device tree matches.  I didn't try to look at your memory in the device tree and compare it to ours to see the differences.

 

The ramdisk doesn't matter at this point, til you get the kernel booting further, or verify it is booting and you have no console.

 

Have you gone thru the wiki at  http://xilinx.wikidot.com/debugging-kernel-boot-problems?

 

This is the best place to start.  I would compare your device tree to the 405 device tree we have in the kernel tree.  That device tree in the kernel tree works fine on a 10.1 EDK system which looks like what your using to generate your system.  For 11.1 and newer, there can be core version compatibility issues with the new cores and the drivers, but we fixed that in the latest device tree generator.

 

Good luck, keep digging,

John

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Hi John,

  Thanks for your suggestion. I have already referred to the mentioned link.

 

As suggestion, I have compared my .dts file with virtex405-ml405.dts file which is provided with the kernel package..

 

The significant difference I found were

 

  1. PLB driver version. The Virtex405-ml405.dts file contains PLB bus compatible with plb-v46-1.02.a. I have updated my EDK 10.1 version with service pack 3. So, my PLB bus version is plb-v46-1.03.a
  2. ML405 board uses DDR memory and my Custom board uses DDR2 Memory. In Virtex405-ml405.dts file, mpmc module is under plb tree where as in my .dts tree, it is under ppc405_0_dplb1 tree. I have connected MPMC module to Processor with point to point PLB(Xilinx connects this way by default) , not in a shared PLB bus like other devices.

 

Is it because of the above reason?

 

Please find the code pasted below

 

 

 

Virtex405-ml405.dts

------------------------------

 

        plb: plb@0 {

                #address-cells = <1>;

                #size-cells = <1>;

                compatible = "xlnx,plb-v46-1.02.a", "simple-bus";

                ranges ;

 

             ………..

             ………..

                mpmc@0 {

                        #address-cells = <1>;

                        #size-cells = <1>;

                        compatible = "xlnx,mpmc-4.00.a";

                        PIM2: sdma@84600100 {

                                compatible = "xlnx,ll-dma-1.00.a";

                                interrupt-parent = <&xps_intc_0>;

                                interrupts = < 1 2 0 2 >;

                                reg = < 0x84600100 0x80 >;

                        } ;

             ………..

             ………..

 

};

 

 

my.dts

---------

 

        ppc405_0_dplb1: plb@1 {

                #address-cells = <1>;

                #size-cells = <1>;

                compatible = "xlnx,plb-v46-1.03.a", "simple-bus";

                ranges ;

                mpmc@0 {

                        #address-cells = <1>;

                        #size-cells = <1>;

                        compatible = "xlnx,mpmc-4.03.a";

                } ;

        } ;

 

 

Apart from above stated differences, I don’t find any significant differences.

 

Please find my complete .dts file in my  first post of this thread.

 

It will be of great help if you provide more suggestions.

 

Thanks

Rajesh RV


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Hi John,

  Just to update, i had made some progress in booting up the linux kernel,

 

The Problem was with UART port. In my custom board, i dont have a RS232 Interface. So, i have connected it to the general purpose IOs and create RS232-TTL level shifter described in the link below.

 

http://sodoityourself.com/max232-serial-level-converter/

 

STD-OUT is working fine. But , looks like there is some troble in STD-IN mode.

 

In arch/powerpc/boot/main.c, i found that it is getting struct at line where bootstapper opens the console in edit mode.

 

static void prep_cmdline(void *chosen)
{
        if (cmdline[0] == '\0')
                getprop(chosen, "bootargs", cmdline, COMMAND_LINE_SIZE-1);

        printf("\n\rLinux/PowerPC load: %s", cmdline);
        /* If possible, edit the command line */
//      if (console_ops.edit_cmdline)
//              console_ops.edit_cmdline(cmdline, COMMAND_LINE_SIZE);

        printf("\n\r");

        /* Put the command line back into the devtree for the kernel */
        setprop_str(chosen, "bootargs", cmdline);
}
 

I have commented out those lines and now it starts executing the kernel,  Now, i got struct at next level.

 

The processor gets into exeception when executing _memset_io function. The PC switches between real address <-> Virtual Address.

 

I checked my RS232 connection. Electrically, it looks good. I'll  debug further by writing simple program to read from Hyperterminal.

 

Meanwhile, can you throw some light on the exeception because of _memset_io function. Is it due to RS232 again ????

 

I know its not good to debug software when there is problem with Hardware.  But, some knowldge on _memset_io function could help.

 

Thanks

Rajesh RV

 

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rajeshrv wrote:

And i edited it to enable Xilinx UART and made it as console by running "make menuconfig"

 

I have downloaded 8MB ramdisk image from this forum and placed in arch/powerpc/boot dir

 

I have configured my block ram as 8192 in my kernel.

 

Pleasef find my .config file attached


Could you tell me the link for the 8MB ramdisk image?

 

Simon

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