Hi,
I have created the attached design, starting from the design provided in xilinx-zcu102-v2016.4-final1.bsp
I have added three PCS/PMA cores, and connected them to the SFP+ connectors.
After exporting the hardware from Vivado, and importing them into Petalinux, I get the attached Petalinux project.
The compiled Linux image boots correctly with:
petalinux-boot --jtag --fpga --bitstream images/linux/design_1_wrapper.bit --kernel
But unfortunately the PCS/PMA based PHYs are not recognized (below is the related part of the boot log):
[ 3.322719] libphy: Fixed MDIO Bus: probed [ 3.327260] tun: Universal TUN/TAP device driver, 1.6 [ 3.332284] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> [ 3.338601] CAN device driver interface [ 3.343172] macb ff0b0000.ethernet: invalid hw address, using random [ 3.349527] gpiod_set_value: invalid GPIO [ 3.353917] libphy: MACB_mii_bus: probed [ 3.360544] macb ff0b0000.ethernet eth0: no PHY found [ 3.404512] macb ff0c0000.ethernet: invalid hw address, using random [ 3.410856] gpiod_set_value: invalid GPIO [ 3.415220] libphy: MACB_mii_bus: probed [ 3.421849] macb ff0c0000.ethernet eth0: no PHY found [ 3.460497] macb ff0d0000.ethernet: invalid hw address, using random [ 3.466847] gpiod_set_value: invalid GPIO [ 3.471209] libphy: MACB_mii_bus: probed [ 3.474629] ata2: SATA link down (SStatus 0 SControl 330) [ 3.474659] ata1: SATA link down (SStatus 0 SControl 330) [ 3.488703] macb ff0d0000.ethernet eth0: no PHY found [ 3.528494] gpiod_set_value: invalid GPIO [ 3.532800] libphy: MACB_mii_bus: probed [ 3.540111] macb ff0e0000.ethernet eth0: Cadence GEM rev 0x50070106 at 0xff0e0000 irq 33 (00:0a:35:00:02:90) [ 3.549975] TI DP83867 ff0e0000.etherne:0c: attached PHY driver [TI DP83867] (mii_bus:phy_addr=ff0e0000.etherne:0c, irq=-1) [ 3.561766] usbcore: registered new interface driver asix
In the final dts file all Ethernet controllers are described as follows:
ethernet@ff0b0000 {
compatible = "cdns,zynqmp-gem";
status = "okay";
interrupt-parent = <0x2>;
interrupts = <0x0 0x39 0x4 0x0 0x39 0x4>;
reg = <0x0 0xff0b0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
#stream-id-cells = <0x1>;
iommus = <0x6 0x874>;
power-domains = <0xc>;
clocks = <0xd 0xd 0xd>;
phy-mode = "gmii";
xlnx,ptp-enet-clock = <0x0>;
linux,phandle = <0x1f>;
phandle = <0x1f>;
};
ethernet@ff0c0000 {
compatible = "cdns,zynqmp-gem";
status = "okay";
interrupt-parent = <0x2>;
interrupts = <0x0 0x3b 0x4 0x0 0x3b 0x4>;
reg = <0x0 0xff0c0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
#stream-id-cells = <0x1>;
iommus = <0x6 0x875>;
power-domains = <0xe>;
clocks = <0xd 0xd 0xd>;
phy-mode = "gmii";
xlnx,ptp-enet-clock = <0x0>;
linux,phandle = <0x20>;
phandle = <0x20>;
};
ethernet@ff0d0000 {
compatible = "cdns,zynqmp-gem";
status = "okay";
interrupt-parent = <0x2>;
interrupts = <0x0 0x3d 0x4 0x0 0x3d 0x4>;
reg = <0x0 0xff0d0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
#stream-id-cells = <0x1>;
iommus = <0x6 0x876>;
power-domains = <0xf>;
clocks = <0xd 0xd 0xd>;
phy-mode = "gmii";
xlnx,ptp-enet-clock = <0x0>;
linux,phandle = <0x21>;
phandle = <0x21>;
};
ethernet@ff0e0000 {
compatible = "cdns,zynqmp-gem";
status = "okay";
interrupt-parent = <0x2>;
interrupts = <0x0 0x3f 0x4 0x0 0x3f 0x4>;
reg = <0x0 0xff0e0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
#stream-id-cells = <0x1>;
iommus = <0x6 0x877>;
power-domains = <0x10>;
clocks = <0xd 0xd 0xd>;
phy-mode = "rgmii-id";
xlnx,ptp-enet-clock = <0x0>;
local-mac-address = [00 0a 35 00 02 90];
phy-handle = <0x11>;
linux,phandle = <0x22>;
phandle = <0x22>;
phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
linux,phandle = <0x11>;
phandle = <0x11>;
};
};
Only the third one, that uses the external PHY is operational.
Should I add the phy definitions for the PCS/PMA connected controllers myself?
TIA & Regards,
Wojtek
PS. The attached files should be renamed to des_plnx.tar.xz and xilinx-zcu102-2016.4_xpr_zip, respectively.
I was not able to post them with original names (they were rejected with complaint, that extension does not match the contents).
1 Solution
Accepted Solutions
Xilinx published the new XAPP1305 note mentioned here: http://www.wiki.xilinx.com/PS+and+PL+based+Ethernet+in+Zynq+MPSoC
Unfortunately, the design files are not available yet: https://forums.xilinx.com/t5/UltraScale-Architecture/Where-are-design-files-for-XAPP-1305/td-p/745318
I'm trying to anayze the Zynq Ultrascale+ TRM in hope that I'll find the solution myself.
It is still unclear how to connect the GMII_ENETx ports in PS with GMII_GEM_PCS_PMA ports, as they contain different pins (in PS there are additional rx_clk, tx_clk, crs,col and speed_mode lines). Splitting the ports and connecting lines by hand make design illegible and difficult to maintain. Below is just a part of the design in it's last form (I also attach the VEXTPROJ version of the design):
Now I have added the GPIO cores to monitor the PCS/PMA status and to reset PCS/PMA.
Unfortunately I still get the PCS/PMA status 0x806 after booting the system.
When I reset the PCS/PMA, the status starts to oscillate between: 0x818, 0x810, 0x850, and 0x870.
I have checked different settings of PCS/PMA - SGMII, 1000BaseX, with and without autonegotiation and with and without "SGMII PHY mode".
I use GLC-T compatible transceivers:
Regards,
Wojtek
