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Observer aroytman
Observer
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Registered: ‎12-07-2017

ZCU102 - loading bitstream

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Hello expets,

 

I need to download bitstream for a proprietary RTOS.
Following the procedure in ug1085, chapter 11, section named "Configuration Programming Model".
I need this to be non-secure.

The CPU is in ARM7 mode - 32bit.

 

The problem is that I get "Data abort" exception on reading & writing to CSU pcap_reset register.

The RTOS image is loaded by a pre-built u-boot (from Petalinux) over network (TFTP).
So, is it possible that it loads & locks the SSS and prevents reconfiguration of PL?

Here is information I've collected:

Note that registers have virtual addresses and the mapping is correct:

 

VIRTUAL ADDR BLOCK LENGTH PHYSICAL ADDR PROT (S/U) CACHE SPECIAL
------------ ------------ ------------- ---------- -------- ------------
0x221b9000 0x00006000 0x00ffca0000 RW- / --- OFF/CO/G -- <<------- non-cached, coherent, guarded. Physical address is of CSU.

 

---------------------------------------------------------------------------------
Current Processor Status Register: 0x80000013 <<-------------- 8 - overflow in last operation, 13 - b10011 = Supervisor mode

<<<<<Registers>>>>>

r0 = 0x00000020 r1 = 0x221b9044 r2 = 0x22006000
r3 = 0x00000000 r4 = 0x00000000 r5 = 0x00000000
r6 = 0x00000000 r7 = 0x00000000 r8 = 0xffffffff
r9 = 0x202a1fb8 r10 = 0x202a1fc8 r11/fp = 0x20243ddc
r12/ip = 0xffffffff r13/sp = 0x202a1f78 r14/lr = 0x0028fa60
pc = 0x003e66b0 cpsr = 0x80000013 ttbase = 0x00000000
tlsbase = 0x00000000

<<<<<Disassembly>>>>>

003e6690 e5910000 LDR r0,[r1,#0]
003e6694 e1a0f00e MOV pc,lr
003e6698 e1a00000 NOP
003e669c e1a00000 NOP
003e66a0 e1a00000 NOP
003e66a4 e1a00000 NOP
003e66a8 e1a00000 NOP
003e66ac e1a00000 NOP
*003e66b0 e5910000 LDR r0,[r1,#0] <<<<------------- exception is here
003e66b4 f57ff04f CLREX
003e66b8 e1a0f00e MOV pc,lr
003e66bc e1a00000 NOP
003e66c0 e1a00000 NOP
003e66c4 e1a00000 NOP
003e66c8 e1a00000 NOP
003e66cc e1a00000 NOP
---------------------------------------------------------------------------------

 

Also, I've found some mismatch between code that SDK uses for Isolation restore & corresponding registers definition.
To illustrate, here is the code snippet from SDK (XFpga_IsolationRestore in xilfpga_pcap.c):

+++++++++++
/* Isolation request enable */

Xil_Out32(PMU_GLOBAL_ISO_INT_EN, PMU_GLOBAL_PWR_PL_MASK);


/* Trigger Isolation request */

Xil_Out32(PMU_GLOBAL_ISO_TRIG, PMU_GLOBAL_PWR_PL_MASK);

 

/* Poll for Isolation complete */

PollCount = (PL_DONE_POLL_COUNT);

do {

        RegVal = Xil_In32(PMU_GLOBAL_ISO_STATUS) & PMU_GLOBAL_PWR_PL_MASK;

        PollCount--;

} while ((RegVal != 0) && PollCount);

+++++++++++

 

Note that in SDK PMU_GLOBAL_PWR_PL_MASK is: #define PMU_GLOBAL_PWR_PL_MASK 0x800000
Looking at ug1087 for registers PMU_GLOBAL_ISO_INT_EN, PMU_GLOBAL_ISO_TRIG and PMU_GLOBAL_ISO_STATUS
seems that PMU_GLOBAL_PWR_PL_MASK should be 0x4.

 

Appreciate any help.

Thank you

 

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Scholar austin
Scholar
2,966 Views
Registered: ‎02-27-2008

Re: ZCU102 - loading bitstream

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So that is confusing (to me),

 

How is it loaded?  Unless the A53 is doing the loading, how can it have configured 32 bit mode?  I expect the 32 bit executable needs to be wrapped in a 64 bit wrapper (to place the A53 in the correct mode)?  Not sure what the sequence of operation is here, and what brings in the 32 bit executable code, and how it is expected to start in 32 bit mode.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Scholar austin
Scholar
2,014 Views
Registered: ‎02-27-2008

Re: ZCU102 - loading bitstream

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The ZCU102 has 4 A53 processors, 2 R5, no A7.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer aroytman
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Registered: ‎12-07-2017

Re: ZCU102 - loading bitstream

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I am talking about A53 in 32 bit mode, aka ARM7 compatible.

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Scholar austin
Scholar
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Registered: ‎02-27-2008

Re: ZCU102 - loading bitstream

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"

3.3. Changing execution state

There are times when you must change the execution state of your system. This could be, for example, if you are running a 64-bit operating system, and want to run a 32-bit application at EL0. To do this, the system must change to AArch32."

 

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/CHDIHCJE.html

 

You cannot 'just execute' the 32 bit binary.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer aroytman
Observer
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Registered: ‎12-07-2017

Re: ZCU102 - loading bitstream

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The RTOS is already running. It is a 32 bit one. So, the switch of execution state has already occurred at early stage of RTOS boot.

However, just to mention: it is loaded by a 64 bit u-boot.

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Scholar austin
Scholar
2,967 Views
Registered: ‎02-27-2008

Re: ZCU102 - loading bitstream

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So that is confusing (to me),

 

How is it loaded?  Unless the A53 is doing the loading, how can it have configured 32 bit mode?  I expect the 32 bit executable needs to be wrapped in a 64 bit wrapper (to place the A53 in the correct mode)?  Not sure what the sequence of operation is here, and what brings in the 32 bit executable code, and how it is expected to start in 32 bit mode.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer aroytman
Observer
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Registered: ‎12-07-2017

Re: ZCU102 - loading bitstream

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U-boot loads the executable, i.e. the RTOS.
As you guessed, RTOS is wrapped in 64 bit wrapper that places the A53 in 32 bit mode. Once the switch is done, all the rest is in 32 bit mode. RTOS boots and runs w/o problems.

Now, it is time to load the bitstream. The code has no problems when accessing PMU GLOBAL registers. However, some CSU access needs to be done as well (per ug1085) before triggering the CSUDMA transfer.

An attempt to access a CSU register triggers the exception.

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Scholar austin
Scholar
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Registered: ‎02-27-2008

Re: ZCU102 - loading bitstream

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The bitstream is loaded by copying from the SD card to the device?

 

with $: cat file_path/led.bit.bin > /dev/xdevcfg

 

I expect that refers to a device driver that isn't in your 32 bit linux build.  So how did you re-code this driver in your linux that is now running?

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer aroytman
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Registered: ‎12-07-2017

Re: ZCU102 - loading bitstream

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My RTOS is not Linux. It is a commercial RTOS.

The bitstream file is brought into memory by FTP client that this RTOS includes. It is placed into block of memory that is not cached, coherent and guarded.

I want to trigger CSUDMA to perform the transfer. Basically, (I think) this is the way it is done by Linux (from ug1085: The PCAP is the only interface used to configure the PL during
normal operating conditions.")

The actual steps the driver takes are per ug1085, chapter 11.
The relevant section is named "Configuration Programming Model".
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Scholar austin
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Registered: ‎02-27-2008

Re: ZCU102 - loading bitstream

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OK,

 

I get the picture now.  Never done that, so I am unable to help you there.  In non-secure mode, the configuration requires access to the PCAP, so I do not know what the CSU has to do to get at the PCAP once it thinks it has finished and is no longer needed.  It probably released PCAP use to whomever ....  not sure how that works (to get to PCAP again).

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer aroytman
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Registered: ‎12-07-2017

Re: ZCU102 - loading bitstream

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I believe it must be doable, e.g. for partial reconfiguration.

Thank you for looking into this.
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Scholar austin
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Registered: ‎02-27-2008

Re: ZCU102 - loading bitstream

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The PR flow,

 

as supported, doesn't involve switching to 32 bit mode.  So, looking at the PR flow may not help.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer aroytman
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Registered: ‎12-07-2017

Re: ZCU102 - loading bitstream

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What PR stands for?
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Scholar austin
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Registered: ‎02-27-2008

Re: ZCU102 - loading bitstream

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partial reconfiguration

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer aroytman
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Registered: ‎12-07-2017

Re: ZCU102 - loading bitstream

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OK, I understand. However, I am trying to do full reconfiguration.

Anyway, accessing CSU registers should not trigger Data abort.
At this point I would like to find a way to understand what went wrong, i.e. why Data abort is triggered.
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Scholar austin
Scholar
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Registered: ‎02-27-2008

Re: ZCU102 - loading bitstream

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Agreed,


The CSU has 'ownership' of the PCAP, unless released to the A53, or R5's.  So check if any code has executed to remove the PCAP from CSU control.


Austin

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer aroytman
Observer
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Registered: ‎12-07-2017

Re: ZCU102 - loading bitstream

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Not sure where to look. Is there a register in CSU where this information resides? Which one?

The problem at this time is that I cannot access CSU registers at all. Even reading the version register triggers Data abort.
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Observer aroytman
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Registered: ‎12-07-2017

Re: ZCU102 - loading bitstream

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I cannot not find where the 'ownership' is set.
Could you please provide a pointer?

Thank you
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Scholar austin
Scholar
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Registered: ‎02-27-2008

Re: ZCU102 - loading bitstream

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a,

 

That is a hard coded function, part of the security, so I don't think you can affect it.  I have requested someone more familiar with these details to look at your question.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Moderator
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Registered: ‎12-04-2016

Re: ZCU102 - loading bitstream

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Hi

We usually observe abort when we try to access CSU register through devmem in linux:-

 #devmem 0xFFCA0044
[ 457.530558] Unhandled fault: synchronous external abort (0x92000010) at 0x0000007fa0dcd044
Bus error

 

To access the CSU, we have to use the command as follows by enabling the PM in Linux
echo "MMIO_READ 0xFFCA0044" > /sys/kernel/debug/zynqmp_pm/power

 

 

Best Regards

Shabbir

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Observer aroytman
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Registered: ‎12-07-2017

Re: ZCU102 - loading bitstream

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I guess this implies that debugfs is configured. Doesn't it?

 

Does thus request go through ATF?

 

The goal it to do this programaticaly.

It was mentioned earlier in this thread that there is some notion of 'ownership' of the PCAP by the CSU.

I would like to understand how it is set and whether it can be passed to an OS running on A53.

 

Thank you

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Visitor akhikhlukha
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Registered: ‎04-10-2018

Re: ZCU102 - loading bitstream

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Hello,

 

Did you manage to find a solution? I've faced with the same issue. Any attempt to read CSU registers is leading to bus error. I assume it could be read through the smc call but it is not convenient way for me.

 

Thanks in advance.

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