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Observer mnsgs
Observer
391 Views
Registered: ‎05-23-2017

Zynq-7000 DDR ECC Verification Using Linux 4.14 EDAC Driver

Hi,

On a custom design, based on z7030, I am trying to verify the DDR ECC functionality based on https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842241/EDAC+Driver which unfortunately appears somewhat outdated. SW baseline is Linux 4.14 booted using u-boot, which indicates that the init code exported from Vivado 2018r2 indeed enables ECC:

Board: Xilinx Zynq
Silicon: v3.1
DRAM: ECC enabled 512 MiB

The following is observed:

$ dmesg | grep -i edac
EDAC MC: Ver: 3.0.0
EDAC MC0: Giving out device to module 1 controller synps_ddr_controller: DEV synps_edac (POLLED)

$ cat /proc/device-tree/amba/memory-controller@f8006000/compatible
xlnx,zynq-ddrc-a05

$ tail -c 0 -f /var/log/messages &
$ devmem2 0x1F400000 w 0x5D600000
/dev/mem opened.
Memory mapped at address 0xb6f33000.
Read at address 0x1F400000 (0xb6f33000): 0x5D600001
Write at address 0x1F400000 (0xb6f33000): 0x5D600000, readback 0x5D600000

$ cat /sys/devices/system/edac/mc/mc0/ce_count && cat /sys/devices/system/edac/mc/mc0/ue_count
0
0

Any idea what is wrong here?

 

Regards,

Martin

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8 Replies
Xilinx Employee
Xilinx Employee
347 Views
Registered: ‎04-15-2011

回复: Zynq-7000 DDR ECC Verification Using Linux 4.14 EDAC Driver

@mnsgs Do you enable CONFIG_EDAC_SYNOPSYS? And can you share your realted devicetree node?

And can you share your PS DDR settings in Vivado?

Once I have your information, I would like to check it on Xilinx board.

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Observer mnsgs
Observer
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Registered: ‎05-23-2017

回复: Zynq-7000 DDR ECC Verification Using Linux 4.14 EDAC Driver

Hi @longley ,

Appreciate your response. 

Yes, the kernel config is indeed enabled (also proven by the dmesg output). The device-tree includes Xilinx zynq-7000.dtsi from ADI fork https://github.com/analogdevicesinc/linux/tree/adi-4.14.0 and we thus inherit the default memory controller config. Reverse compiling the loaded device tree yields:

dtc -I dtb -O dts nanocom-sdr-z7030-nv2-a.dtb | grep 'f8006000 {' -A 4

memory-controller@f8006000 {
    compatible = "xlnx,zynq-ddrc-a05";
    reg = <0xf8006000 0x1000>;
    phandle = <0x16>;
};

It is also verified that logging is enabled through the edac core:
$ cat /sys/module/edac_core/parameters/edac_mc_log_*
1
1

Attached is a screenshot of the vivado html report - is this what you seek?

For your information, we have been successfully running this setup for a few years now, but would like to capture any ECC erros occurring during operation.

vivado-ddr.png
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Observer mnsgs
Observer
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Registered: ‎05-23-2017

回复: Zynq-7000 DDR ECC Verification Using Linux 4.14 EDAC Driver

Hi @longley ,

Any update on the topic? 

As a sidenote I can confirm that the zynqmp procesdure works on zcu102. This makes sense to me as the procedure involves intructing the controller to poison the data, which is not the case for the zynq and I thus doubt how this will ever work?

Thanks,

Martin

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Xilinx Employee
Xilinx Employee
274 Views
Registered: ‎04-15-2011

回复: Zynq-7000 DDR ECC Verification Using Linux 4.14 EDAC Driver

@mnsgs 

Sorry for the delay update. I can see the same behavior as yours in 2018.3 and 2019.1, and am asking the writer of this EDAC page. And I haven't heard updates right now. I suppose we should update this wiki pages. 

And from the source code of , it looks like inserting ECC error is only supported for MPSoC device. 

If there is any update, I will get back to this thread. 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-15-2011

回复: Zynq-7000 DDR ECC Verification Using Linux 4.14 EDAC Driver

@mnsgs 

Please check the EDAC wiki page again. I think it is updated.

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Observer mnsgs
Observer
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Registered: ‎05-23-2017

回复: Zynq-7000 DDR ECC Verification Using Linux 4.14 EDAC Driver

Hi @longley ,

Thanks for the update, unfortunately I am not able to reproduce the outcome of the updated instructions. With the updated PS7 init code, u-boot indicates the expected reduced memory amount:

U-Boot 2018.01-00021-g7531b42e8f-dirty (Oct 25 2019 - 08:59:46 +0000)
Model: Gomspace NanoMind NV2
Board: Xilinx Zynq
Silicon: v3.1
DRAM: ECC enabled 500 MiB

which is also confirmed from Linux:

$ free
total used free shared buffers cached
Mem: 497032 63676 433356 8480 3096 39176
-/+ buffers/cache: 21404 475628
Swap: 0 0 0

$ cat /proc/device-tree/memory@0/reg | hexdump
0000000 0000 0000 401f 0000
0000008

Driver is indeed loaded

$ dmesg | grep -i edac
EDAC MC: Ver: 3.0.0
EDAC MC0: Giving out device to module 1 controller synps_ddr_controller: DEV synps_edac (POLLED)

Reading the memory address beyond the 500MB does not trigger any detection:

$ devmem2 0x1F500000
/dev/mem opened.
Memory mapped at address 0xb6ff7000.
Read at address 0x1F500000 (0xb6ff7000): 0x00000000

$ root@nanomind-z7000-nv2:~# cat /sys/devices/system/edac/mc/mc0/ce_count && cat /sys/devices/system/edac/mc/mc0/ue_count
0
0

Any ideas?

 

Thanks,

Martin

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Xilinx Employee
Xilinx Employee
128 Views
Registered: ‎04-15-2011

回复: Zynq-7000 DDR ECC Verification Using Linux 4.14 EDAC Driver

Hi, Martin,
I try in 2018.3 Petalinux, and can see the expected output of the updated test procedure.
After you modify ps7_init code, please clean FSBL project and build again.
You can double check the assemble code of FSBL if necessary. And make sure you use the new FSBL when packaging boot image.

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Observer mnsgs
Observer
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Registered: ‎05-23-2017

回复: Zynq-7000 DDR ECC Verification Using Linux 4.14 EDAC Driver

Hi @longley ,

Sorry for the delay - I did not get a notification for your reply.

I feel confident that the amount of memory actually is reduced - as stated above,it is printed by u-boot:

DRAM: ECC enabled 500 MiB

and also through the 'free' command in Linux:

$ free
total used free shared buffers cached
Mem: 497032 63676 433356 8480 3096 39176
-/+ buffers/cache: 21404 475628
Swap: 0 0 0

(I also introduced a compiler error that actually the compilation to make sure the actual source file is indeed the one built by the compiler)

Note, that I am not using XSDK to render the FSBL, instead u-boot is rendering the SPL based on the exported ps7init code.

 

Regards,

Martin

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