Zynq Petalinux hangs on GPIO access

[c.mcclenaghan]

Hello all

I've been having a problem accessing GPIO on a Zedboard using a custom configuration and Petalinux build.

Vivado 2015.2

Petalinux 2015.2

CentOS 7

Zedboard Rev C

TLDR

I have connected the LEDs, switches and buttons using AXI_GPIO blocks to look like the reference designs from Avnet (including the correct pins from the schematic). They appear in the device tree as I expect but when I attempt to access them, the PS appears to hang - no response to the serial terminal, no response to ping from PC etc. It needs a PS [button] reset to recover.

I'd appreciate any suggestions on this. I'm pretty sure I was able to use the LEDs and switches using the reference images when I first got the board so I believe my steps to be correct ... barring something silly, of course :).

Details

As far as I can tell, I've enabled the GPIO options in the kernel config:

$ grep GPIO subsystems/linux/configs/kernel/config | grep -v ^#
CONFIG_ARCH_NR_GPIO=1024
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_GPIO_POLLED=y
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_DEVRES=y
CONFIG_OF_GPIO=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_GPIO_XILINX=y
CONFIG_GPIO_ZYNQ=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGER_GPIO=y

 and the devicetree (also attached in full) shows the following:

$ less subsystems/linux/configs/device-tree/pl.dtsi 

/ {
 amba_pl: amba_pl {
 #address-cells = <1>;
 #size-cells = <1>;
 compatible = "simple-bus";
 ranges ;

<snip>

  leds_8bits: gpio@41210000 {
    #gpio-cells = <2>;
    compatible = "xlnx,xps-gpio-1.00.a";
    gpio-controller ;
    reg = <0x41210000 0x10000>;
    xlnx,all-inputs = <0x0>;
    xlnx,all-inputs-2 = <0x1>;
    xlnx,all-outputs = <0x1>;
    xlnx,all-outputs-2 = <0x0>;
    xlnx,dout-default = <0x00000000>;
    xlnx,dout-default-2 = <0x00000000>;
    xlnx,gpio-width = <0x8>;
    xlnx,gpio2-width = <0x5>;
    xlnx,interrupt-present = <0x0>;
    xlnx,is-dual = <0x0>;
    xlnx,tri-default = <0xFFFFFFFF>;
    xlnx,tri-default-2 = <0xFFFFFFFF>;
  };

<snip>

 };
};

On board boot-up (from QSPI flash, incidently) I can see the following:

<snip>
GPIO IRQ not connected

XGpio: /amba_pl/gpio@41200000: registered, base is 901

GPIO IRQ not connected

XGpio: /amba_pl/gpio@41210000: registered, base is 893

GPIO IRQ not connected

XGpio: /amba_pl/gpio@41220000: registered, base is 885
<snip>

Serial terminal to Zedboard:

~# cd /sys/class/gpio/
/sys/class/gpio# ls
export       gpiochip885  gpiochip893  gpiochip901  gpiochip906  unexport

/sys/class/gpio# cat gpiochip893/label
/amba_pl/gpio@41210000

/sys/class/gpio# cat gpiochip893/ngpio 
8

/sys/class/gpio# echo 893 > export 
/sys/class/gpio# ls
export gpiochip885 gpiochip901 unexport
gpio893 gpiochip893 gpiochip906

/sys/class/gpio# echo 1 > gpio893/value 
-sh: echo: write error: Operation not permitted

/sys/class/gpio# cat gpio893/direction
in

/sys/class/gpio# echo out > gpio893/direction
<hangs here - needs PS reset to recover>

...

<Try again, reading this time with the above setup>

/sys/class/gpio# cat gpio893/value
<hangs here again - needs PS reset to recover>

When I build the kernel with debugging:

/sys/class/gpio# cat /sys/kernel/debug/gpio
GPIOs 885-892, /amba_pl/gpio@41220000:

GPIOs 893-900, /amba_pl/gpio@41210000:

GPIOs 901-905, /amba_pl/gpio@41200000:

GPIOs 906-1023, platform/e000a000.gpio, zynq_gpio:

Shouldn't there be more information here? e.g. similar to this page.

Again, I'd appreciate any insight or similar experiences.

Many thanks.

Regards

Chris

[muzaffer]

are you sure you enabled the fclk necessary for pl in the ps7 configuration in vivado? is pl being programmed correctly? is done led on?

[c.mcclenaghan]

Hi

The DONE LED is lit showing the FPGA has configured. I also checked it by programming the FPGA directly from SDK after the board boots. That seemed to succeed as well.

I will check my Vivado project for the clock settings.

Thanks

Chris

[c.mcclenaghan]

Hi

I've attached a screenshot of my configuration. Highlighted is the FCLK_CLK0 net. Note I'm not using any interrupts back from the PL but I don't think this should matter in this particular case.

Here is the clock configurations - the FCLK_CLK0 is enabled and set to 100MHz.

Regarding the kernel debugging output, I believe one possiblility for this being empty (see original question) is the drivers have not loaded correctly, e.g. if they were modules to load after boot, but I see the Xgpio sections of the start-up messages so I assume these are loaded as built-ins.

Thanks

Chris

[etelm]

Hi,

in the same spirit,

With Board zc702
Petalinux 2015.2,

Create a new project from bsp file ,

petalinux-create -t project -s ./Xilinx-ZC702-v2015.2-final.bsp -n test703

After copy the content of the subfolder 'test703/pre-built/linux/images' on a SD-card,

The system start correctly,

After logon a simple:

poke 0x41200000 0   will hangs the system,

I tried this project after some tests with other board and projects coming from vivado,

It's always the same,

For me the problem comes from the FCLK_CLK0, this signal disappear after the boot,

The system hang because this clock is used by the AXI interfaces.

Before I used petalinux 2014.2, it was ok for this function.

All tests are ok with standalone os.

Best regards.

Gérard.

[c.mcclenaghan]

Hi

Yes. I've narrowed it down to the FCLK as well. I noticed that FCLK is disabled (presumably).

$ tail subsystems/linux/configs/device-tree/pcw.dtsi
};
&usb0 {
        dr_mode = "host";
        phy_type = "ulpi";
        status = "okay";
};
&clkc {
        fclk-enable = <0x0>;
        ps-clk-frequency = <33333333>;
};

If I create two blank projects with Petalinux 2014.4 and 2015.2 and compare these files I see the 2014.4 one is set as

fclk-enable = <0xf>;

Perhaps the 0xf relates to the 4 FCLK settings available in Vivado?

If I manually change this value to 0xf and rebuild, the GPIO access no longer hangs. I also confirmed

# poke 0x41200000 0xAA

 works as well :)

I don't know if it is related, but I also discovered that when running 

petalinux-config --get-hw-description ....

in 2015.2, the system.hwh (the hardware handover file) is not extracted from the system_wrapper.hdf as it is in 2014.4. (Yes, it is present in the .hdf so it looks like Vivado is correct.)

Could this be a bug in petalinux-config?

So, unless there is a setting I'm missing in the Petalinux configuration, it looks like I'll have to manually update the pcw.dtsi. I'll need to contact Xilinx support to confirm.

Regards

Chris

[etelm]

Hi Chris,

Thank you for the information,

After manual modification,
It's working  for me too,

I don't see the changes made in the Zynq registers,

Best regards,

Gérard.

[c.mcclenaghan]

Possibly some insight here:

http://forums.xilinx.com/t5/Embedded-Linux/enable-PL-clock-outputs/m-p/645886/highlight/true#M13720

I've created a Xilinx service request to get further advice.

Regards

Chris

[achutha · Accepted solution]

@c.mcclenaghan

The 2015.1 version of the device tree generator (DTG) does not seem to properly parse the HDF (i.e. PL design) file and determine which FCLKs (0, 1, 2, 3) are enabled. The resulting entry in the dts file is set to 0x0:

&clkc {

fclk-enable = <0x0>;

ps-clk-frequency = <33333333>;

};

This causes the Linux kernel to hang when we try to talk to the PL (i.e. any soft IP block) because none of the PL clocks are enabled.

To work around the issue we simply override the fclk-enable entry and set it to 0xf.

There is already a change request (CR# 869424) raised on this and this is fixed in 2015.3 release.

Regards,

Achutha

[umer.sabeen]

Hello

I am also using zedboard  7z020

my pl.dtsi is same like yours.

I found /sys/class/gpio/gpiochip906/ under gpiochip906

cat base
906

cat label 
zynq_gpio

cat ngpio
118

but when i am trying to generate

root@Avnet-Digilent-ZedBoard-2015_2:/sys/class/gpio# echo 65>export 

root@Avnet-Digilent-ZedBoard-2015_2:/sys/class/gpio# ls
export       gpiochip906  unexport
root@Avnet-Digilent-ZedBoard-2015_2:/sys/class/gpio# 

can you help me where i am doing mistake

thanks

Sana

[linnj]

Have you gone thru this page in detail?

http://www.wiki.xilinx.com/Linux+GPIO+Driver

[umer.sabeen]

Hello linnj 

I want to tell you some detail about my project. I want to send /receive data from Spi and GPIO, 

I was using windows 7 and centos i clone the kernal and u-bootand activate the spi

make menuconfig ->device driver ->SPI support -> then enabled xilinx SPI controller common module and user mode spi

I read in tuturail "There is no device tree generator yet for Zynq yet such that hand editing the device tree is the current method."  so i just add these line in the zynq-zed.dts and convert it into dtb

&spi0 {

status = "okay";
}

and in zynq-7000.dtsi 

spidev@0x01 {
compatible = "spidev0.2";
spi-max-frequency = <20000000>;
reg = <1>;
};

but after running the board

the enviroment is like this I can see spidev after that i tried to transfer data by gpio (simplest case) but i cannot create any gpio node after the following command

root# echo 61>/sys/class/gpio/export

but no gpio connected .

someone in the forum told me that i should move to linux and use petalinux

Now I am using ubuntu 14.04 ,vivado 2015.2 and petalinux.BSP 2015.2 version and working for Xilinx Zedboard 7z020

I created my project and generate the .hdf and .bit file after that export it to SDK

then I create a project using defined BSP

$petalinux-create -t project -s /Downloads/Avnet-2015.2.BSP

get the hardware

$ petalinux-config --get-hw-description=~/my_program/my_program.sdk

run petalinux configuration

$petalinux-config

subsystem Auto hardware setting->Advance bootable image storage setting and select sd-card for boot image ,kernel image and dtb image setting

in the system-top.dts I add the lines

build the images

$petalinux-build

generate BOOT.BIN:

$petalinux-package --boot --format BIN --fsbl ~/Avnet-Digilent-ZedBoard-2015.2/images/linux/zynq_fsbl.elf --fpga ~my_program/my_program.sdk/system_wrapper_hw_platform_0/system_wrapper.bit --u-boot

generate rootfs.cpio with the following command because I want to boot the board with sd-card

$petalinux-package --image -c rootfs --format initramfs

IN the sd card copy BOOT.BIN , image.ub and system.dtb into BOOT partition and rootfs.cpio into rootfs partition then run the following command

$sudo pax -rvf rootfs.cpio

In the last boot the board with this sd card

and the result is, I cannot find any /dev/spidev

then i tried to check the gpio then same problem

Now you are saying to follow the

http://www.wiki.xilinx.com/Linux+GPIO+Driver

I think problem is in devicetree

should i follow this or 

http://www.wiki.xilinx.com/Build+Device+Tree+Blob

I have to make changes in after editing the system-top.dts (petalinux) or zynq-zed.dts(cent os)

which one is better?

hope you understand my problem

thanks

[sorenb]

---

@umer.sabeen wrote:

Hello

I am also using zedboard  7z020

my pl.dtsi is same like yours.

I found /sys/class/gpio/gpiochip906/ under gpiochip906

cat base
906

cat label 
zynq_gpio

cat ngpio
118

but when i am trying to generate

root@Avnet-Digilent-ZedBoard-2015_2:/sys/class/gpio# echo 65>export 

root@Avnet-Digilent-ZedBoard-2015_2:/sys/class/gpio# ls
export       gpiochip906  unexport
root@Avnet-Digilent-ZedBoard-2015_2:/sys/class/gpio# 

can you help me where i am doing mistake

thanks

Sana

---

With base = 906 and ngpio = 118 the valid GPIO numbers are in the range from 906 to 1023 for this GPIO device. Unless some other device is in that range, 65 is not a avlid GPIO number.

[umer.sabeen]

thanks for your reply

it solved my problem at some extent

please have a look at the following code

root@zynq:/sys/class/gpio# echo 1018 > export 
root@zynq:/sys/class/gpio# cd gpio1018
root@zynq:/sys/class/gpio/gpio1018# echo out > direction 
root@zynq:/sys/class/gpio/gpio1018# echo 1 > value       
root@zynq:/sys/class/gpio/gpio1018# cat value 
0
root@zynq:/sys/class/gpio/gpio1018# cat direction 
out

why after echo 1 > value the value of the file is not changing at all

thanks in advance