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Visitor mjgeorge
Visitor
94 Views
Registered: ‎02-11-2019

axi_quad_spi integration problem in Petalinux 2017.4

I am having trouble getting a PL SPI (axi_quad_spi). My project is using a ZU9 running Petalinux 2017.4. When I boot the system I get the following errors during Linux kernel initialization:

[ 2.276172] xilinx_spi 80000000.axi_quad_spi: can't setup spi4.0, status -13
[ 2.283135] spi_master spi4: spi_device register error /amba_pl@0/axi_quad_spi@80000000/ad9361-phy@0
[ 2.292247] spi_master spi4: Failed to create SPI device for /amba_pl@0/axi_quad_spi@80000000/ad9361-phy@0

The following is the auto-generated device tree information for the axi_quad_spi:

axi_quad_spi_0: axi_quad_spi@80000000 {
   bits-per-word = <8>;
   compatible = "xlnx,xps-spi-2.00.a";
   fifo-size = <16>;
   interrupt-parent = <&gic>;
   interrupts = <0 95 1>;
   num-cs = <0x1>;
   reg = <0x0 0x80000000 0x0 0x10000>;
   xlnx,num-ss-bits = <0x1>;
   xlnx,spi-mode = <0>;
};

 

We are setting up an alias of spi4 for the axi_quad_spi.

aliases {
   ...
   spi4 = &axi_quad_spi_0;
};

 

To that, we add an AD9361 device on the axi_quad_spi interface. The final device tree looks like the following:

axi_quad_spi@80000000 {
   bits-per-word = <0x8>;
   compatible = "xlnx,xps-spi-2.00.a";
   fifo-size = <0x10>;
   interrupt-parent = <0x4>;
   interrupts = <0x0 0x60 0x4>;
   num-cs = <0x1>;
   reg = <0x0 0x80000000 0x0 0x10000>;
   xlnx,num-ss-bits = <0x1>;
   xlnx,spi-mode = <0x0>;
   status = "okay";

   ad9361-phy@0 {
      #address-cells = <0x1>;
      #size-cells = <0x0>;
      #clock-cells = <0x1>;
      compatible = "ad9361";
      reg = <0x0>;
      spi-cpha;
      spi-max-frequency = <0x989680>;
      clocks = <0x37 0x0>;
      clock-names = "ad9361_ext_refclk";
      clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
      adi,digital-interface-tune-skip-mode = <0x0>;
      adi,pp-tx-swap-enable;
      adi,pp-rx-swap-enable;
      adi,rx-frame-pulse-mode-enable;
      adi,lvds-mode-enable;
      adi,lvds-bias-mV = <0x96>;
      adi,lvds-rx-onchip-termination-enable;
      adi,rx-data-delay = <0x4>;
      adi,tx-fb-clock-delay = <0x7>;
      adi,dcxo-coarse-and-fine-tune = <0x8 0x1720>;
      adi,2rx-2tx-mode-enable;
      adi,frequency-division-duplex-mode-enable;
      adi,rx-rf-port-input-select = <0x0>;
      adi,tx-rf-port-input-select = <0x0>;
      adi,tx-attenuation-mdB = <0x2710>;
      adi,rf-rx-bandwidth-hz = <0x112a880>;
      adi,rf-tx-bandwidth-hz = <0x112a880>;
      adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
      adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
      adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
      adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
      adi,gc-rx1-mode = <0x2>;
      adi,gc-rx2-mode = <0x2>;
      adi,gc-adc-ovr-sample-size = <0x4>;
      adi,gc-adc-small-overload-thresh = <0x2f>;
      adi,gc-adc-large-overload-thresh = <0x3a>;
      adi,gc-lmt-overload-high-thresh = <0x320>;
      adi,gc-lmt-overload-low-thresh = <0x2c0>;
      adi,gc-dec-pow-measurement-duration = <0x2000>;
      adi,gc-low-power-thresh = <0x18>;
      adi,mgc-inc-gain-step = <0x2>;
      adi,mgc-dec-gain-step = <0x2>;
      adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
      adi,agc-attack-delay-extra-margin-us = <0x1>;
      adi,agc-outer-thresh-high = <0x5>;
      adi,agc-outer-thresh-high-dec-steps = <0x2>;
      adi,agc-inner-thresh-high = <0xa>;
      adi,agc-inner-thresh-high-dec-steps = <0x1>;
      adi,agc-inner-thresh-low = <0xc>;
      adi,agc-inner-thresh-low-inc-steps = <0x1>;
      adi,agc-outer-thresh-low = <0x12>;
      adi,agc-outer-thresh-low-inc-steps = <0x2>;
      adi,agc-adc-small-overload-exceed-counter = <0xa>;
      adi,agc-adc-large-overload-exceed-counter = <0xa>;
      adi,agc-adc-large-overload-inc-steps = <0x2>;
      adi,agc-lmt-overload-large-exceed-counter = <0xa>;
      adi,agc-lmt-overload-small-exceed-counter = <0xa>;
      adi,agc-lmt-overload-large-inc-steps = <0x2>;
      adi,agc-gain-update-interval-us = <0x3e8>;
      adi,**bleep**c-dec-pow-measurement-duration = <0x40>;
      adi,**bleep**c-lp-thresh-increment-steps = <0x1>;
      adi,**bleep**c-lp-thresh-increment-time = <0x5>;
      adi,**bleep**c-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
      adi,**bleep**c-final-overrange-count = <0x3>;
      adi,**bleep**c-gain-index-type-after-exit-rx-mode = <0x0>;
      adi,**bleep**c-lmt-final-settling-steps = <0x1>;
      adi,**bleep**c-lock-level = <0xa>;
      adi,**bleep**c-lock-level-gain-increase-upper-limit = <0x5>;
      adi,**bleep**c-lock-level-lmt-gain-increase-enable;
      adi,**bleep**c-lpf-final-settling-steps = <0x1>;
      adi,**bleep**c-optimized-gain-offset = <0x5>;
      adi,**bleep**c-power-measurement-duration-in-state5 = <0x40>;
      adi,**bleep**c-rst-gla-engergy-lost-goto-optim-gain-enable;
      adi,**bleep**c-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
      adi,**bleep**c-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
      adi,**bleep**c-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
      adi,**bleep**c-rst-gla-large-adc-overload-enable;
      adi,**bleep**c-rst-gla-large-lmt-overload-enable;
      adi,**bleep**c-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
      adi,**bleep**c-rst-gla-stronger-sig-thresh-exceeded-enable;
      adi,**bleep**c-state-wait-time-ns = <0x104>;
      adi,**bleep**c-use-last-lock-level-for-set-gain-enable;
      adi,rssi-restart-mode = <0x3>;
      adi,rssi-delay = <0x1>;
      adi,rssi-wait = <0x1>;
      adi,rssi-duration = <0x3e8>;
      adi,ctrl-outs-index = <0x0>;
      adi,ctrl-outs-enable-mask = <0xff>;
      adi,temp-sense-measurement-interval-ms = <0x3e8>;
      adi,temp-sense-offset-signed = <0xce>;
      adi,temp-sense-periodic-measurement-enable;
      adi,aux-dac-manual-mode-enable;
      adi,aux-dac1-default-value-mV = <0x0>;
      adi,aux-dac1-rx-delay-us = <0x0>;
      adi,aux-dac1-tx-delay-us = <0x0>;
      adi,aux-dac2-default-value-mV = <0x0>;
      adi,aux-dac2-rx-delay-us = <0x0>;
      adi,aux-dac2-tx-delay-us = <0x0>;
      enable-gpios = <0x38 0x4e 0x0>;
      txnrx-gpios = <0x38 0x4f 0x0>;
      ctrl_in0-gpios = <0x38 0x50 0x0>;
      ctrl_in1-gpios = <0x38 0x51 0x0>;
      ctrl_in2-gpios = <0x38 0x52 0x0>;
      ctrl_in3-gpios = <0x38 0x53 0x0>;
      en_agc-gpios = <0x38 0x54 0x0>;
   };
};

 

Any help would be appreciated.

 

 

 

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4 Replies
Xilinx Employee
Xilinx Employee
59 Views
Registered: ‎06-27-2017

Re: axi_quad_spi integration problem in Petalinux 2017.4

Hi @mjgeorge,

Can you give a try with 256 as fifo size?

 fifo-size = <0x100>;

Best Regards
Kranthi
--------------------------
Don't forget to reply, kudo, and accept as solution.
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Visitor mjgeorge
Visitor
43 Views
Registered: ‎02-11-2019

Re: axi_quad_spi integration problem in Petalinux 2017.4

I tried with the fifo-size set to 256, but there was no change in the results.

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Xilinx Employee
Xilinx Employee
30 Views
Registered: ‎06-27-2017

Re: axi_quad_spi integration problem in Petalinux 2017.4

Hi @mjgeorge,

Please refer below forum post for reference. This is due to not handling power management properly.

https://forums.xilinx.com/t5/Embedded-Linux/SPIDEV-problems-on-Xilinx-Linux-2017-1/m-p/774078#M20198

Either you can suspend the PM using disabling CONFIG_PM or add the work-around patch suggested in link.

 

Best Regards
Kranthi
--------------------------
Don't forget to reply, kudo, and accept as solution.
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Visitor mjgeorge
Visitor
20 Views
Registered: ‎02-11-2019

Re: axi_quad_spi integration problem in Petalinux 2017.4

Ok. I had seen that thread, but it was very confusing as it offered several solutions, none of which seemed to work consistently for everyone who posted on that thread.  A few follow-up questions:

1. Could you provide a little more background explanation as to what is going on so I can understand it better?

2. Which is the preferred solution from Xilinx perspective?

3. If there really is a driver bug the the linked patch is the correct fix for it, why has that patch never been incorporated into the master branch?

4. Has Xilinx verified the correctness of the patch you linked to? If I am going to use that patch, I want to make sure it's technically correct.

Thanks,

Matthew

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