UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Reply

enable PL clock outputs

Accepted Solution Solved
Adventurer
Posts: 86
Registered: ‎06-05-2014
Accepted Solution

enable PL clock outputs

In my Vivado design I have two clock output going to the PL from the Zyzq block. The frist is FCLK_CLK0 at 100 MHz and the second is FCLK_CLK1 at 25 MHz. When I boot my kernel it doesn't appear that FCLK_CLK1 is enabled.

 

I'm assuming I need to modify my device tree to enable the second clock output?


Accepted Solutions
Adventurer
Posts: 86
Registered: ‎06-05-2014

Re: enable PL clock outputs

Thanks for the responses. My problem was I couldn't see where in the dts the FCLK_CLK outputs were set up. (I actually still can't find this.) But, I think I was just using the wrong bitfile as it appears to be working.

 

I have the FCLK_CLK1 going into a clocking wizard and the locked output going to an LED to indicate whether the clock is active. I'm using 3.19 from meta-xilinx as my build environment. 

 

At any rate, I'm going to mark this solved. But, I'm now curious whether these clocks are set up in hardware (that's what appears to be the case) or via the device tree. And if it's device tree what the the dts entry would look like. thanks.

View solution in original post


All Replies
Xilinx Employee
Posts: 1,128
Registered: ‎07-01-2010

Re: enable PL clock outputs

@clutch12

 

Do you had a chance to check the clock outputs during the baremetal test?

 

If it is working with baremetal test, the dts details should have been populated automatically.

 

How did you confirm if FCLK1 is not enabled ?

 

Are you using open source linux or petalinux ?

 

Regards,

Achutha

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------
Moderator
Posts: 1,901
Registered: ‎07-23-2012

Re: enable PL clock outputs

Yes, you need to enable FCLK_CLK1 in devicetree to enable FSCLK_CLK1 during the boot.
-----------------------------------------------------------------------------------------------
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

Give Kudos to a post which you think is helpful.
Adventurer
Posts: 86
Registered: ‎06-05-2014

Re: enable PL clock outputs

Thanks for the responses. My problem was I couldn't see where in the dts the FCLK_CLK outputs were set up. (I actually still can't find this.) But, I think I was just using the wrong bitfile as it appears to be working.

 

I have the FCLK_CLK1 going into a clocking wizard and the locked output going to an LED to indicate whether the clock is active. I'm using 3.19 from meta-xilinx as my build environment. 

 

At any rate, I'm going to mark this solved. But, I'm now curious whether these clocks are set up in hardware (that's what appears to be the case) or via the device tree. And if it's device tree what the the dts entry would look like. thanks.

Xilinx Employee
Posts: 444
Registered: ‎03-13-2012

Re: enable PL clock outputs

Nothing is set up in HW (well sure, everything has some reset values, but that's it). You set the clocks up in the configuration wizard in Vivado. That configuration propagatest to the FSBL (export HW and the FSBL consumes the hdf file).

Hence, every time you do changes in PCW you have to export the design again and rebuild your FSBL.

The FSBL will then initialize all clocks etc. according to that configuration, giving it the boot up state.

Once Linux comes up, Linux is in charge. Linux expects that clocks are used through its clock framework. I.e. drivers in the OS enable/disable clocks etc. Clocks that are not enabled within this framework will be disabled after boot.

If you have HW that depends on the FCLKs but does not have a driver in Linux, you can still use the FCLKs as static clock generators by specifying the 'fclk-enable' property in your device tree (https://www.kernel.org/doc/Documentation/devicetree/bindings/clock/zynq-7000.txt)

 

Adventurer
Posts: 86
Registered: ‎06-05-2014

Re: enable PL clock outputs

@sorenb wow, thanks. Yes, that explains it. I had rebuilt my fsbl this morning so that's obviously what caused my clocks to work. You've saved me a lot of aggravation. Thanks again.