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wzhang1
Observer
Observer
1,702 Views
Registered: ‎02-21-2018

how to disable L2 cache on APU of ZCU102

Hi,

 

I like to compare the performance on the APU of ZCU102 production board with L2 cache enabled and disabled.

 

I am assuming L2 cache is enabled by default on APU. (Correct me if I am wrong.) Then the question is how to disable L2 cache. I am even not sure if this is possible or not.

 

After some research, it looks like to me that it is possible to remove L2 cache in the device-tree. But I couldn't find the corresponding node there.

 

Thanks!

 

 

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6 Replies
sandeepg
Moderator
Moderator
1,674 Views
Registered: ‎04-24-2017

Hi @wzhang1,

 

Yes you can disable only if the device-tree entry for CPU has this properties https://www.devicetree.org/downloads/devicetree-specification-v0.1-20160524.pdf or else you can't.

 

AFAIK we don't have these properties in device-tree.

Thanks,
Sandeep
PetaLinux Yocto | Embedded SW Support

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sandeepg
Moderator
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Registered: ‎04-24-2017

Someone had already done for Zynq7000 https://secbus.telecom-paristech.fr/wiki/DisablingZynqCaches 

Thanks,
Sandeep
PetaLinux Yocto | Embedded SW Support

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wzhang1
Observer
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Registered: ‎02-21-2018

Thank you very much for your reply, Sandeep!

 

I searched for device tree configuration in my petalinux project. No L2 cache entry was found. 

 

However, I found the following stuff under the folder of "project-spec".

 

1. in ./meta-plnx-generated/recipes-bsp/u-boot/configs/config.cfg:

CONFIG_SYS_L2CACHE_OFF is not set

 

What is CONFIG_SYS_L2CHACHE_OFF for? Is it for turning ON/OFF L2 cache on APU?

 

2. in ./configs/rootfs_config:

CONFIG_ccache is not set

CONFIG_ccache-dbg is not set 

CONFIG_ccache-dev is not set

CONFIG_udev-cache is not set

CONFIG_menu-cache is not set

CONFIG_menu-cache-dbg is not set

CONFIG_menu-cache-dev is not set

 

What are these options for? Would you please give me some information about them? 

 

Thanks!

Wei

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sonminh
Adventurer
Adventurer
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Registered: ‎10-02-2018

Hi @wzhang1 , @sandeepg ,

I'm need to disable cache on zc706 run petalinux.

have you try disable cache ?

Can you heclp me?

Thanks

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sandeepg
Moderator
Moderator
796 Views
Registered: ‎04-24-2017

Hi @sonminh ,

Take a look on this wiki https://gitlab.telecom-paris.fr/renaud.pacalet/secbus/wikis/disabling-zynq-caches

Thanks,
Sandeep
PetaLinux Yocto | Embedded SW Support

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sonminh
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Registered: ‎10-02-2018

I just try implement as you talk but no have any change once boot petalinux 2017.4 on zc706:

1. In file xilinx_zynq_defconfig of external linux  (components/ext_sources/linux-xlnx-2017.4_video_ea/arch/arm/configs), I add in to end of file:

CONFIG_CPU_ICACHE_DISABLE=y
CONFIG_CPU_DCACHE_DISABLE=y

2. petalinux-config -c kernel --defconfig xilinx_zynq_defconfig 

3. petalinux-build -c kernel

4. Modify file system-user.dtsi in /project-spec/meta-user/recipes-bsp/device-tree/files:

/include/ "system-conf.dtsi"
/ {
};
&amba {
cache-controller@f8f02000 {
status = "disabled";
};
};

5. Petalinux-build

This is my device-tree after disable cache and build:

cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xf8f02000 0x1000>;
interrupts = <0x0 0x2 0x4>;
arm,data-latency = <0x3 0x2 0x2>;
arm,tag-latency = <0x2 0x2 0x2>;
cache-unified;
cache-level = <0x2>;
status = "disabled";
};

But once boot with BOOT.bin and image.ub just build, L2 cache still enable and I don't know veryfy that L1 is disabled. I see time to boot still fast. Here is console once boot linux, L2 cache still probe although disable.

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
Booting Linux on physical CPU 0x0
Linux version 4.9.0-xilinx (thanhnt@ubuntu) (gcc version 6.2.1 20161016 (Linaro GCC 6.2-2016.11) ) #1 SMP PREEMPT Sat Nov 16 14:11:29 +07 2019
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5287d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt:Machine model: Zynq ZC706 Development Board
bootconsole [earlycon0] enabled
cma: Reserved 16 MiB at 0x3f000000
Memory policy: Data cache writealloc
percpu: Embedded 14 pages/cpu @ef7cb000 s25932 r8192 d23220 u57344
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 260608
Kernel command line: console=ttyPS0,115200 earlyprintk
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1007240K/1048576K available (6144K kernel code, 200K rwdata, 1464K rodata, 1024K init, 230K bss, 24952K reserved, 16384K cma-reserved, 245760K highmem)
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
    lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .text : 0xc0008000 - 0xc0700000   (7136 kB)
      .init : 0xc0900000 - 0xc0a00000   (1024 kB)
      .data : 0xc0a00000 - 0xc0a32180   ( 201 kB)
       .bss : 0xc0a32180 - 0xc0a6b998   ( 231 kB)
Preemptible hierarchical RCU implementation.
        Build-time adjustment of leaf fanout to 32.
        RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2
NR_IRQS:16 nr_irqs:16 16
efuse mapped to f0802000
slcr mapped to f0804000
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
zynq_clock_init: clkc starts at f0804100
Zynq clock init

Can you talk clearly? Thank you

 

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